cpu/intel/car: Define post codes

This moves a lot of post code values, but unifies them between
platforms, so that the same value means the same thing as much as
possible.

The P4-netburst code was the most extensive and most different, so that
dictated the majority of the values.  Three were two values there that
didn't match the other files, so those two values, 0x22 & 0x29 have
duplicate entries in the table.

The rest of the entries are similar between platforms, though the values
for many of them were moved to match the P4-netburst values.

POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become
global, while POST_SOC would be specific to the Intel platforms.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69866
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 21 insertions, 19 deletions

diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 9ac9e22c3e..01abdf884f 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/intel/post_codes.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
@@ -19,7 +20,7 @@ _cache_as_ram_setup:
 bootblock_pre_c_entry:
 
 cache_as_ram:
-	post_code(0x20)
+	post_code(POST_BOOTBLOCK_CAR)
 
 	movl	$LAPIC_BASE_MSR, %ecx
 	rdmsr
@@ -52,7 +53,7 @@ clear_var_mtrr:
 	inc	%ecx
 	dec	%ebx
 	jnz	clear_var_mtrr
-	post_code(0x21)
+	post_code(POST_SOC_SET_DEF_MTRR_TYPE)
 
 	/* Configure the default memory type to uncacheable. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -60,7 +61,7 @@ clear_var_mtrr:
 	andl	$(~0x00000cff), %eax
 	wrmsr
 
-	post_code(0x22)
+	post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS)
 
 	/* Determine CPU_ADDR_BITS and load PHYSMASK high
 	 * word to %edx.
@@ -104,7 +105,7 @@ addrsize_set_high:
 
 bsp_init:
 
-	post_code(0x23)
+	post_code(POST_SOC_BSP_INIT)
 
 	/* Send INIT IPI to all excluding ourself. */
 	movl	LAPIC(ICR), %edi
@@ -118,7 +119,7 @@ bsp_init:
 	andl	$LAPIC_ICR_BUSY, %ecx
 	jnz	1b
 
-	post_code(0x24)
+	post_code(POST_SOC_COUNT_CORES)
 
 	movl	$1, %eax
 	cpuid
@@ -153,7 +154,7 @@ cores_counted:
 
 hyper_threading_cpu:
 
-	post_code(0x25)
+	post_code(POST_SOC_CPU_HYPER_THREADING)
 
 	/* Send Start IPI to all excluding ourself. */
 	movl	LAPIC(ICR), %edi
@@ -168,7 +169,7 @@ hyper_threading_cpu:
 	andl	$LAPIC_ICR_BUSY, %ecx
 	jnz	1b
 
-	post_code(0x26)
+	post_code(POST_SOC_CPU_SIBLING_DELAY)
 
 	/* Wait for sibling CPU to start. */
 1:	movl	$(MTRR_PHYS_BASE(0)), %ecx
@@ -184,14 +185,14 @@ hyper_threading_cpu:
 
 
 ap_init:
-	post_code(0x27)
+	post_code(POST_SOC_CPU_AP_INIT)
 
 	/* Do not disable cache (so BSP can enable it). */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	movl	%eax, %cr0
 
-	post_code(0x28)
+	post_code(POST_SOC_SET_MTRR_BASE)
 
 	/* MTRR registers are shared between HT siblings. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
@@ -199,7 +200,7 @@ ap_init:
 	xorl	%edx, %edx
 	wrmsr
 
-	post_code(0x29)
+	post_code(POST_SOC_AP_HALT)
 
 ap_halt:
 	cli
@@ -210,7 +211,7 @@ ap_halt:
 
 sipi_complete:
 
-	post_code(0x2a)
+	post_code(POST_SOC_SET_CAR_BASE)
 
 	/* Set Cache-as-RAM base address. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
@@ -226,7 +227,7 @@ sipi_complete:
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
-	post_code(0x2b)
+	post_code(POST_SOC_ENABLE_MTRRS)
 
 	/* Enable MTRR. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -269,7 +270,7 @@ has_msr_11e:
 	wrmsr
 no_msr_11e:
 
-	post_code(0x2c)
+	post_code(POST_SOC_ENABLE_CACHE)
 
 	/* Cache the whole rom to fetch microcode updates */
 	movl	$MTRR_PHYS_BASE(1), %ecx
@@ -296,7 +297,7 @@ no_msr_11e:
 	jmp	update_bsp_microcode
 	end_microcode_update:
 #endif
-	post_code(0x2d)
+	post_code(POST_SOC_DISABLE_CACHE)
 	/* Disable caching to change MTRR's. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
@@ -336,7 +337,7 @@ cache_rom:
 	wrmsr
 
 fill_cache:
-	post_code(0x2e)
+	post_code(POST_SOC_FILL_CACHE)
 	/* Enable cache. */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -379,7 +380,7 @@ fill_cache:
 #endif
 
 before_c_entry:
-	post_code(0x2f)
+	post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
 	call	bootblock_c_entry_bist
 
 	/* Should never see this postcode */
diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S
index 108342ff3c..1684407e81 100644
--- a/src/cpu/intel/car/p4-netburst/exit_car.S
+++ b/src/cpu/intel/car/p4-netburst/exit_car.S
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/intel/post_codes.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
@@ -10,14 +11,14 @@
 chipset_teardown_car:
 	pop %esp
 
-	post_code(0x30)
+	post_code(POST_POSTCAR_DISABLE_CACHE)
 
 	/* Disable cache. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
 
-	post_code(0x31)
+	post_code(POST_POSTCAR_DISABLE_DEF_MTRR)
 
 	/* Disable MTRR. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -25,7 +26,7 @@ chipset_teardown_car:
 	andl	$(~MTRR_DEF_TYPE_EN), %eax
 	wrmsr
 
-	post_code(0x32)
+	post_code(POST_POSTCAR_TEARDOWN_DONE)
 
 	/* Return to caller. */
 	jmp	*%esp