diff options
| author | Yuchen He <yuchenhe126@gmail.com> | 2023-07-25 21:28:36 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-05 16:04:46 +0000 |
| commit | 1e67adbc73e30be098ce163e3d27a7a7ecf68ae0 (patch) | |
| tree | a2880851ac6c754d94fc056472beb5ec133ab0b4 /src/cpu/intel/car/non-evict | |
| parent | 71b8ee0da407158d51eb7d86a6e1d4c458fc8e96 (diff) | |
src/*/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
src/include/cpu/intel/post_codes.h \
src/soc/intel/common/block/include/intelblocks/post_codes.h"
array=`grep -r "#define POST_" $header | \
tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`
for str in $array; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r $str src | cut -d ':' -f 1 | \
xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done
Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/cpu/intel/car/non-evict')
| -rw-r--r-- | src/cpu/intel/car/non-evict/cache_as_ram.S | 16 | ||||
| -rw-r--r-- | src/cpu/intel/car/non-evict/exit_car.S | 6 |
2 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 187b1ca9e2..18ac07036e 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -34,14 +34,14 @@ wait_for_sipi: bt $12, %eax jc wait_for_sipi - post_code(POST_SOC_SET_DEF_MTRR_TYPE) + post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE) /* Clean-up MTRR_DEF_TYPE_MSR. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr - post_code(POST_SOC_CLEAR_FIXED_MTRRS) + post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list, %ebx xor %eax, %eax @@ -88,7 +88,7 @@ addrsize_set_high: movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(POST_SOC_SET_MTRR_BASE) + post_code(POSTCODE_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl car_mtrr_start, %eax @@ -96,7 +96,7 @@ addrsize_set_high: xorl %edx, %edx wrmsr - post_code(POST_SOC_SET_MTRR_MASK) + post_code(POSTCODE_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -117,7 +117,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(POST_SOC_ENABLE_MTRRS) + post_code(POSTCODE_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -188,7 +188,7 @@ end_microcode_update: orl $3, %eax wrmsr - post_code(POST_SOC_DISABLE_CACHE) + post_code(POSTCODE_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -199,7 +199,7 @@ end_microcode_update: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(POST_SOC_ENABLE_CACHE) + post_code(POSTCODE_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -234,7 +234,7 @@ end_microcode_update: #endif before_c_entry: - post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 56370f8841..9e37b4644c 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -13,14 +13,14 @@ chipset_teardown_car: pop %esp - post_code(POST_POSTCAR_DISABLE_CACHE) + post_code(POSTCODE_POSTCAR_DISABLE_CACHE) /* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(POST_POSTCAR_DISABLE_DEF_MTRR) + post_code(POSTCODE_POSTCAR_DISABLE_DEF_MTRR) /* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -36,7 +36,7 @@ chipset_teardown_car: andl $~1, %eax wrmsr - post_code(POST_POSTCAR_TEARDOWN_DONE) + post_code(POSTCODE_POSTCAR_TEARDOWN_DONE) /* Return to caller. */ jmp *%esp |