diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-03-23 00:19:01 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-24 17:34:40 +0000 |
| commit | b017a43a6d31d2babd6170b6adf7712506f776c2 (patch) | |
| tree | d19cfa6eac1154250aea69a8967ae7a7d1fef1d9 /src/cpu/armltd | |
| parent | dd8472e2b6321b2e85a251db51c8d28eb8bb2e3c (diff) | |
soc/intel/common: Add APIs to check CSE's write protection info
The patch add APIs to check CSE Region's write protection information.
Also, adds helper functions to get the SPI controller's MMIO address
to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read
protection details.
During the coreboot image build, write protection is enabled for CSE RO.
It is enabled through a Intel MFIT XML configuration.
TEST=Verify write protection information of CSE Region
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/cpu/armltd')
0 files changed, 0 insertions, 0 deletions