diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-25 11:21:02 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-02 05:11:04 +0000 |
| commit | 903ce25040df2c6eb2856aa89740c49964b573d7 (patch) | |
| tree | f6c5d6a7143c170afcd6c57f0b3653bb393d4842 /src/cpu/amd | |
| parent | dbd64953aeac482976a63a8d56adb9562d5a00e4 (diff) | |
binaryPI: Introduce BINARYPI_LEGACY_WRAPPER and its counterpart
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/agesa/romstage.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/pi/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/amd/pi/Makefile.inc | 7 |
3 files changed, 10 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c index a7d2ff90b7..91c5518207 100644 --- a/src/cpu/amd/agesa/romstage.c +++ b/src/cpu/amd/agesa/romstage.c @@ -131,7 +131,7 @@ void asmlinkage romstage_after_car(void) if (HAS_LEGACY_WRAPPER) agesa_postcar(cb); - if (cb->s3resume) + if (!IS_ENABLED(CONFIG_CPU_AMD_PI) && cb->s3resume) set_resume_cache(); run_ramstage(); diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index c0e942837e..51897b6dd8 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -30,6 +30,9 @@ config CPU_AMD_PI if CPU_AMD_PI +config BINARYPI_LEGACY_WRAPPER + def_bool n + config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 7e3c8c03cc..3171bb5d67 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -19,7 +19,12 @@ subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc +ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) romstage-y += romstage.c +ramstage-y += amd_late_init.c +else +romstage-y += ../agesa/romstage.c +endif + romstage-y += ../agesa/heapmanager.c ramstage-y += ../agesa/heapmanager.c -ramstage-y += amd_late_init.c |