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authorFelix Held <felix-coreboot@felixheld.de>2021-07-13 00:54:32 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-07-14 02:24:39 +0000
commit1b46e76df9ef0a4b38d782732ee914ab70667bfa (patch)
tree83b3471f79037cc7376e2817ddd2905922d4f7eb /src/cpu/amd
parente3f7ef22864402e72e1fa6c1df3bc79199c40bdc (diff)
include/cpu/x86/msr: introduce IA32_MC_*(x) macros
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4 and added to the IA32_MC0_* define to get the MSR number. Add a macro that already does this calculation to avoid open coding this repeatedly. Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c2
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c2
-rw-r--r--src/cpu/amd/agesa/family16kb/model_16_init.c2
-rw-r--r--src/cpu/amd/pi/00730F01/model_16_init.c2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 1bcbc34904..76c8521761 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -63,7 +63,7 @@ static void model_14_init(struct device *dev)
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index c7fcb36c20..883bd59228 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -62,7 +62,7 @@ static void model_15_init(struct device *dev)
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 28c3e78900..f945f80ce1 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -60,7 +60,7 @@ static void model_16_init(struct device *dev)
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 7266a2cc61..3c78c095d0 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -45,7 +45,7 @@ static void model_16_init(struct device *dev)
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
/* Enable the local CPU APICs */
setup_lapic();