diff options
| author | Thejaswani Putta <thejaswani.putta@intel.com> | 2019-08-28 16:23:20 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-19 09:35:51 +0000 |
| commit | 7140db475181722163cea0b4cfce9f12b39506ee (patch) | |
| tree | dc556e5e6b5f01a901d205d8afc57dd3a93a829e /src/cpu/amd/socket_G34/socket_G34.c | |
| parent | ecea91679f3193b308eabcd5f1f82525f0f5669f (diff) | |
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support
1. Add support to read memory strap
2. Add support to configure below memory parameters
-> rcomp resistor configuration
-> dqs mapping
-> ect and ca vref config
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/cpu/amd/socket_G34/socket_G34.c')
0 files changed, 0 insertions, 0 deletions