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authorMarc Jones <marcj303@gmail.com>2012-01-30 19:30:45 -0700
committerMarc Jones <marcj303@gmail.com>2012-02-20 05:37:26 +0100
commitd8d8c63cf71efbc8fae21e3db8aea87b530111f9 (patch)
tree20c62d4d6ff94ede297e9b4dd51e0e71f35954da /src/cpu/amd/socket_C32
parentdc0bdbab2df7ff8c89b0e1325a60ce994ee6bf43 (diff)
Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.
The MTRR check for WB TOM2 setting was only checking revF, not extended family revisions. All families above revf indicate 0xf in the family field and have additional bits in the extended family field. Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/627 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/socket_C32')
0 files changed, 0 insertions, 0 deletions