Initial AMD Barcelona support for rev Bx.

These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 323 insertions, 0 deletions

diff --git a/src/cpu/amd/quadcore/Config.lb b/src/cpu/amd/quadcore/Config.lb
new file mode 100644
index 0000000000..d0dbaadd94
--- /dev/null
+++ b/src/cpu/amd/quadcore/Config.lb
@@ -0,0 +1,20 @@
+#
+# This file is part of the LinuxBIOS project.
+#
+# Copyright (C) 2007 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+object amd_sibling.o
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
new file mode 100644
index 0000000000..4ed770d981
--- /dev/null
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <pc80/mc146818rtc.h>
+#include <smp/spinlock.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/model_10xxx_msr.h>
+#include <cpu/amd/model_10xxx_rev.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern device_t get_node_pci(u32 nodeid, u32 fn);
+
+#if 0
+static int first_time = 1;
+#endif
+
+#include "quadcore_id.c"
+
+static u32 get_max_siblings(u32 nodes)
+{
+	device_t dev;
+	u32 nodeid;
+	u32 siblings=0;
+
+	//get max siblings from all the nodes
+	for(nodeid=0; nodeid<nodes; nodeid++){
+		int j;
+		dev = get_node_pci(nodeid, 3);
+		j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
+		if(siblings < j) {
+			siblings = j;
+		}
+	}
+
+	return siblings;
+}
+
+
+static void enable_apic_ext_id(u32 nodes)
+{
+	device_t dev;
+	u32 nodeid;
+
+	//enable APIC_EXIT_ID all the nodes
+	for(nodeid=0; nodeid<nodes; nodeid++){
+		u32 val;
+		dev = get_node_pci(nodeid, 0);
+		val = pci_read_config32(dev, 0x68);
+		val |= (1<<17)|(1<<18);
+		pci_write_config32(dev, 0x68, val);
+	}
+}
+
+
+u32 get_apicid_base(u32 ioapic_num)
+{
+	u32 apicid_base;
+	u32 siblings;
+	u32 nb_cfg_54;
+
+	u32 disable_siblings = !CONFIG_LOGICAL_CPUS;
+
+	get_option(&disable_siblings, "quad_core");
+
+	siblings = get_max_siblings(sysconf.nodes);
+
+	if(sysconf.bsp_apicid > 0) { // io apic could start from 0
+		return 0;
+	} else if (sysconf.enabled_apic_ext_id)	{ // enabled ext id but bsp = 0
+		return 1;
+	}
+
+	nb_cfg_54 = read_nb_cfg_54();
+
+
+	//contruct apicid_base
+
+	if((!disable_siblings) && (siblings>0) ) {
+		/* for 8 way dual core, we will used up apicid 16:16, actualy
+		   16 is not allowed by current kernel and the kernel will try
+		   to get one that is small than 16 to make io apic work. I don't
+		   know when the kernel can support 256 apic id.
+		   (APIC_EXT_ID is enabled) */
+
+		//4:10 for two way  8:12 for four way 16:16 for eight way
+		//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
+		apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes :  8 * siblings + sysconf.nodes;
+
+	} else {
+		apicid_base = sysconf.nodes;
+	}
+
+	if((apicid_base+ioapic_num-1)>0xf) {
+		// We need to enable APIC EXT ID
+		printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
+		enable_apic_ext_id(sysconf.nodes);
+	}
+
+	return apicid_base;
+}
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
new file mode 100644
index 0000000000..c08b2090ae
--- /dev/null
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef SET_NB_CFG_54
+	#define SET_NB_CFG_54 1
+#endif
+
+#include "cpu/amd/quadcore/quadcore_id.c"
+
+static inline u32 get_core_num_in_bsp(u32 nodeid)
+{
+	u32 dword;
+	dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
+	dword >>= 12;
+	dword &= 3;
+	return dword;
+}
+
+#if SET_NB_CFG_54 == 1
+static inline u8 set_apicid_cpuid_lo(void)
+{
+	// set the NB_CFG[54]=1; why the OS will be happy with that ???
+	msr_t msr;
+	msr = rdmsr(NB_CFG_MSR);
+	msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
+	wrmsr(NB_CFG_MSR, msr);
+
+	return 1;
+}
+#else
+
+static inline void set_apicid_cpuid_lo(void) { }
+
+#endif
+
+
+static inline void real_start_other_core(u32 nodeid, u32 cores)
+{
+	u32 dword;
+
+	printk_debug("Start other core - nodeid: %02x  cores: %02x\n", nodeid, cores);
+
+	/* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
+	   accesses and error logging to core0 */
+	dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44);
+	dword |= 1 << 27;	// NbMcaToMstCpuEn bit
+	pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword);
+	// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
+	dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
+	dword |= 1 << 5;
+	pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword);
+
+	if(cores > 1) {
+		dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
+		dword |= (1 << 0);	// core2
+		if(cores > 2) {		// core3
+			dword |= (1 << 1);
+		}
+		pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
+	}
+}
+
+//it is running on core0 of node0
+static inline void start_other_cores(void)
+{
+	u32 nodes;
+	u32 nodeid;
+
+	// disable quad_core
+	if (read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0)  {
+		printk_debug("Skip additional core init\n");
+		return;
+	}
+
+	nodes = get_nodes();
+
+	for (nodeid = 0; nodeid < nodes; nodeid++) {
+		u32 cores = get_core_num_in_bsp(nodeid);
+		printk_debug("init node: %02x  cores: %02x \n", nodeid, cores);
+		if (cores > 0) {
+			real_start_other_core(nodeid, cores);
+		}
+	}
+
+}
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
new file mode 100644
index 0000000000..e556d699ab
--- /dev/null
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <arch/cpu.h>
+#include <cpu/amd/quadcore.h>
+#ifdef __ROMCC__
+#include <cpu/amd/model_10xxx_msr.h>
+#endif
+
+//called by bus_cpu_scan too
+u32 read_nb_cfg_54(void)
+{
+	msr_t msr;
+	msr = rdmsr(NB_CFG_MSR);
+	return ( ( msr.hi >> (54-32)) & 1);
+}
+
+static inline u32 get_initial_apicid(void)
+{
+	return ((cpuid_ebx(1) >> 24) & 0xff);
+}
+
+//called by amd_siblings too
+#define CORE_ID_BIT 2
+#define NODE_ID_BIT 6
+struct node_core_id get_node_core_id(u32 nb_cfg_54)
+{
+	struct node_core_id id;
+	u32 core_id_bits;
+
+	u32 ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
+	if(ApicIdCoreIdSize) {
+		core_id_bits = ApicIdCoreIdSize;
+	} else {
+		core_id_bits = CORE_ID_BIT; //quad core
+	}
+
+	// get the apicid via cpuid(1) ebx[31:24]
+	if( nb_cfg_54) {
+		// when NB_CFG[54] is set, nodeid = ebx[31:26], coreid = ebx[25:24]
+		id.coreid = (cpuid_ebx(1) >> 24) & 0xff;
+		id.nodeid = (id.coreid>>core_id_bits);
+		id.coreid &= ((1<<core_id_bits)-1);
+	} else {
+		// when NB_CFG[54] is clear, nodeid = ebx[29:24], coreid = ebx[31:30]
+		id.nodeid = (cpuid_ebx(1) >> 24) & 0xff;
+		id.coreid = (id.nodeid>>NODE_ID_BIT);
+		id.nodeid &= ((1<<NODE_ID_BIT)-1);
+	}
+	return id;
+}
+
+static inline u32 get_core_num(void)
+{
+	return (cpuid_ecx(0x80000008) & 0xff);
+}
+
+static inline struct node_core_id get_node_core_id_x(void) {
+
+	return get_node_core_id( read_nb_cfg_54() );
+}
+