diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-09 00:42:42 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-16 15:23:19 +0100 |
| commit | bf3091bae688606f9cbd69064bf6deeeddb81d1b (patch) | |
| tree | 85c197cdfb74cc12097d1d8377f934b866905c92 /src/cpu/amd/pi | |
| parent | 824416078e2a9d3d38290e4f2efd1809efbcc747 (diff) | |
binaryPI: Fix SSE regression and align stack early
When allowing use of SSE instructions, stack must be
aligned to 16 bytes. Adjust x86 entry to C accordingly,
by pushing values to maintain the alignment.
For some builds, new toolchain and GCC-6.3 could emit
SSE instruction 'andps (%esp),%xmm0' with incorrectly
aligned esp, raising exception and thus preventing boot.
Change-Id: I452d40eadac2b743d0d8431809c9a81bf28c330a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/cpu/amd/pi')
| -rw-r--r-- | src/cpu/amd/pi/cache_as_ram.inc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index 24db6001ea..c0a69ec74a 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -63,6 +63,9 @@ cache_as_ram_setup: AMD_ENABLE_STACK + /* Align the stack. */ + and $0xFFFFFFF0, %esp + #ifdef __x86_64__ /* switch to 64 bit long mode */ mov %esi, %ecx @@ -111,8 +114,6 @@ cache_as_ram_setup: /* Pass the BIST result */ cvtsd2si %xmm0, %edi - /* align the stack */ - and $0xFFFFFFF0, %esp .code64 call cache_as_ram_main @@ -126,6 +127,9 @@ cache_as_ram_setup: /* Restore the cpu_init_detected */ cvtsd2si %xmm1, %ebx + /* Must maintain 16-byte stack alignment here. */ + pushl $0x0 + pushl $0x0 pushl %ebx /* init detected */ pushl %edx /* bist */ call cache_as_ram_main |