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authorAngel Pons <th3fanbus@gmail.com>2020-06-22 18:23:17 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-01 18:15:15 +0000
commit68ab745086c6a062b5cb915424520bd0b18f7849 (patch)
tree2d925bb5401cb455cf703a5e9adb7882cba1f5f9 /src/cpu/amd/pi
parentdd6a3d841b3903a69cacc79890e04ebfe3de5de3 (diff)
nb/intel/ironlake: Simplify BAR handling
Currently, northbridge BARs are 32-bit values. We don't have any use case for BARs above 4 GiB in early stages, so handling possibly 64-bit values seems unnecessary, which currently is a noisy way to write zero. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/amd/pi')
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