cpu/amd/pi: Fix checkpatch warnings and errors

Fix remaining space prohibited between function name and open
parenthesis, line over 80 characters, unnecessary braces for single
statement blocks, space required before open brace errors and warnings
in subdirectories of src/cpu/amd/pi

Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2 files changed, 32 insertions, 26 deletions

diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index 674e5c1cb2..696641c79c 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -25,7 +25,7 @@ void amd_initcpuio(void)
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/* Enable legacy video routing: D18F1xF4 VGA Enable */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
 	PciData = 1;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
@@ -33,29 +33,32 @@ void amd_initcpuio(void)
 	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
 	 * set to non-posted regions.
 	 */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-	PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
-	PciData |= 1 << 7;    /* set NP (non-posted) bit */
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
+	/* last address before processor local APIC at FEE00000 */
+	PciData = 0x00FEDF00;
+	/* set NP (non-posted) bit */
+	PciData |= 1 << 7;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-	PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
+	/* lowest NP address is HPET at FED00000 */
+	PciData = (0xFED00000 >> 8) | 3;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Map the remaining PCI hole as posted MMIO */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
 	PciData = 0x00FECF00; /* last address before non-posted range */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+	LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
 	MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
 	PciData = (UINT32)MsrReg;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Send all IO (0000-FFFF) to southbridge. */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
 	PciData = 0x0000F000;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
 	PciData = 0x00000003;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 }
@@ -68,15 +71,17 @@ void amd_initmmio(void)
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/*
-	  Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-	  Address MSR register.
-	*/
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+	 * Set the MMIO Configuration Base Address and
+	 * Bus Range onto MMIO configuration base
+	 * Address MSR register.
+	 */
+	MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
+		(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
 
 	/* For serial port */
 	PciData = 0xFF03FFD5;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44);
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* PSP */
@@ -86,11 +91,11 @@ void amd_initmmio(void)
 
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
-	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+	LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
 	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
-	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 
-	if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
+	if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
 		LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
 		MsrReg |= 1 << 11;
 		LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index ddea603a6a..0dd720266f 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -41,21 +41,23 @@ static void model_16_init(device_t dev)
 	u32 siblings;
 #endif
 
-	disable_cache ();
+	disable_cache();
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	msr = rdmsr(SYSCFG_MSR);
 	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
 	msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
+	/* BSP: make a0000-bffff UC, c0000-fffff WB,
+	 * same as OntarioApMtrrSettingsList for APs
+	 */
 	msr.lo = msr.hi = 0;
-	wrmsr (0x259, msr);
+	wrmsr(0x259, msr);
 	msr.lo = msr.hi = 0x1e1e1e1e;
 	wrmsr(0x250, msr);
 	wrmsr(0x258, msr);
 	for (msrno = 0x268; msrno <= 0x26f; msrno++)
-		wrmsr (msrno, msr);
+		wrmsr(msrno, msr);
 
 	msr = rdmsr(SYSCFG_MSR);
 	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
@@ -68,9 +70,8 @@ static void model_16_init(device_t dev)
 	/* zero the machine check error status registers */
 	msr.lo = 0;
 	msr.hi = 0;
-	for (i = 0; i < 6; i++) {
+	for (i = 0; i < 6; i++)
 		wrmsr(MCI_STATUS + (i * 4), msr);
-	}
 
 
 	/* Enable the local CPU APICs */