src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam16h PI

Code is based on microcode update procedure from fam10-15h with necessary
microcode blob structure updates for fam16h.

Currently updating microcode in romstage seem to be impossible. AGESA is
overriding the microcode patch regardles of the current microcode revision
patched on CPU. Use ramstage CPU init procedures to update microcode easily.
Tested with microcode blob 07030106 released 2018-02-09 from
platomav/CPUMicrocodes GitHub repository on apu2 platform.

TEST=boot Linux kernel 4.14.50 on PC Engines apu2 and run dmesg to see
patch_level=0x07030106 on all cores

Change-Id: Ic15cba06f3cd9cfbc538b6764b158fa699f0ecf6
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29272
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 58 insertions, 0 deletions

diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c
new file mode 100644
index 0000000000..6acf13a6ef
--- /dev/null
+++ b/src/cpu/amd/pi/00730F01/update_microcode.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2019 PC Engines GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/amd/microcode.h>
+
+struct id_mapping {
+	uint32_t orig_id;
+	uint16_t new_id;
+};
+
+static u16 get_equivalent_processor_rev_id(u32 orig_id)
+{
+	static const struct id_mapping id_mapping_table[] = {
+		/* Family 16h */
+
+	/* TODO This equivalent processor revisions ID needs verification */
+		{ 0x730f01, 0x7301 },
+
+		/* Array terminator */
+		{ 0xffffff, 0x0000 },
+	};
+
+	u32 new_id;
+	int i;
+
+	new_id = 0;
+
+	for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) {
+		if (id_mapping_table[i].orig_id == orig_id) {
+			new_id = id_mapping_table[i].new_id;
+			break;
+		}
+	}
+
+	return new_id;
+}
+
+void update_microcode(u32 cpu_deviceid)
+{
+	u32 equivalent_processor_rev_id =
+				get_equivalent_processor_rev_id(cpu_deviceid);
+	amd_update_microcode_from_cbfs(equivalent_processor_rev_id);
+}