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authorStefan Reinauer <stepan@coresystems.de>2010-06-07 08:29:36 +0000
committerStefan Reinauer <stepan@openbios.org>2010-06-07 08:29:36 +0000
commitaed992054f3af248e12ec88de4c047456fe9b104 (patch)
treef942db029eaba8e209094e75dbdd4c58e0258485 /src/cpu/amd/model_lx/cache_as_ram.inc
parentc4f1a77cd238b106e84d15a4b62e1ffe169e6200 (diff)
replace outb -> port 0x80 with post_code() in some places.
Especially most _smbus functions misuse port 0x80 writes for delays. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_lx/cache_as_ram.inc')
-rw-r--r--src/cpu/amd/model_lx/cache_as_ram.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
index f776a7a727..b592bc51b9 100644
--- a/src/cpu/amd/model_lx/cache_as_ram.inc
+++ b/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -169,8 +169,8 @@ leave_DCacheSetup:
popl %ecx
cmpl %ecx, %edx
je DCacheSetupGood
- movb $0xC5, %al
- outb %al, $0x80
+
+ post_code(0xc5)
DCacheSetupBad:
hlt /* issues */
jmp DCacheSetupBad