diff options
author | Jason Schildt <jschildt@gmail.com> | 2005-08-09 21:53:07 +0000 |
---|---|---|
committer | Jason Schildt <jschildt@gmail.com> | 2005-08-09 21:53:07 +0000 |
commit | 6e44b422b3b26a4ce5b98fca12d0f3ef7d7af110 (patch) | |
tree | 4f94702f435949875bed8f725928cb571b7f40c8 /src/cpu/amd/model_fxx/model_fxx_init.c | |
parent | dc2454eb944c2ea9201bd650d7bc9942d4653a6c (diff) |
- Merge from linuxbios-lnxi (Linux Networx repository) up to public tree.
- Special version for HDAMA rev G with 33Mhz test and reboot out.
- Support for CPU rev E, dual core, memory hoisting,
- corrected an SST flashing problem. Kernel bug work around (NUMA)
- added a Kernel bug work around for assigning CPU's to memory.
r2@gog: svnadmin | 2005-08-03 08:47:54 -0600
Create local LNXI branch
r1110@gog: jschildt | 2005-08-09 10:35:51 -0600
- Merge from Tom Zimmerman's additions to the hdama code for dual core
and 33Mhz fix.
r1111@gog: jschildt | 2005-08-09 11:07:11 -0600
Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL
r1112@gog: jschildt | 2005-08-09 15:09:32 -0600
- temporarily removing hdama tag to update to public repository. Will
reset tag after update.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_fxx/model_fxx_init.c')
-rw-r--r-- | src/cpu/amd/model_fxx/model_fxx_init.c | 98 |
1 files changed, 30 insertions, 68 deletions
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 3c526e78ca..bd3a1cea08 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -21,10 +21,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/mem.h> - -#if CONFIG_LOGICAL_CPUS==1 #include <cpu/amd/dualcore.h> -#endif #include "model_fxx_msr.h" @@ -152,9 +149,6 @@ static void set_init_ecc_mtrrs(void) static void init_ecc_memory(unsigned node_id) { unsigned long startk, begink, endk; -#if K8_E0_MEM_HOLE_SIZEK != 0 - unsigned long hole_startk = 0, hole_endk = 0; -#endif unsigned long basek; struct mtrr_state mtrr_state; device_t f1_dev, f2_dev, f3_dev; @@ -199,25 +193,13 @@ static void init_ecc_memory(unsigned node_id) startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2; endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000; -#if K8_E0_MEM_HOLE_SIZEK != 0 - if (!is_cpu_pre_e0()) { - uint32_t val; - val = pci_read_config32(f1_dev, 0xf0); - if((val & 1)==1) { - hole_startk = ((val & (0xff<<24)) >> 10); - hole_endk = ((val & (0xff<<8))<<(16-10)) - startk; - hole_endk += hole_startk; - } - } -#endif - /* Don't start too early */ begink = startk; if (begink < CONFIG_LB_MEM_TOPK) { begink = CONFIG_LB_MEM_TOPK; } - printk_debug("Clearing memory %uK - %uK: ", startk, endk); + printk_debug("Clearing memory %uK - %uK: ", begink, endk); /* Save the normal state */ save_mtrr_state(&mtrr_state); @@ -234,9 +216,6 @@ static void init_ecc_memory(unsigned node_id) unsigned long size; void *addr; -#if K8_E0_MEM_HOLE_SIZEK != 0 - if ((basek >= hole_startk) && (basek < hole_endk)) continue; -#endif /* Report every 64M */ if ((basek % (64*1024)) == 0) { /* Restore the normal state */ @@ -340,6 +319,7 @@ static inline void k8_errata(void) /* Erratum 91 prefetch miss is handled in the kernel */ + /* Erratum 106 ... */ msr = rdmsr_amd(LS_CFG_MSR); msr.lo |= 1 << 25; @@ -350,7 +330,7 @@ static inline void k8_errata(void) msr.hi |= 1 << (43 - 32); wrmsr_amd(BU_CFG_MSR, msr); - if(is_cpu_d0()) { + if (is_cpu_pre_e0() && !is_cpu_pre_d0()) { /* Erratum 110 ...*/ msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES); msr.hi |=1; @@ -362,26 +342,34 @@ static inline void k8_errata(void) msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); msr.hi |=1; wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + + /* Erratum 113 ... */ + msr = rdmsr_amd(BU_CFG_MSR); + msr.hi |= (1 << 16); + wrmsr_amd(BU_CFG_MSR, msr); } /* Erratum 122 */ - msr = rdmsr(HWCR_MSR); - msr.lo |= 1 << 6; - wrmsr(HWCR_MSR, msr); + if (!is_cpu_pre_c0()) { + msr = rdmsr(HWCR_MSR); + msr.lo |= 1 << 6; + wrmsr(HWCR_MSR, msr); + } + + /* Erratum 123? dual core deadlock? */ + + /* Erratum 131 */ + msr = rdmsr(NB_CFG_MSR); + msr.lo |= 1 << 20; + wrmsr(NB_CFG_MSR, msr); } -void model_fxx_init(device_t dev) +void model_fxx_init(device_t cpu) { unsigned long i; msr_t msr; -#if CONFIG_LOGICAL_CPUS struct node_core_id id; - unsigned siblings; - id.coreid=0; -#else - unsigned nodeid; -#endif /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -404,43 +392,18 @@ void model_fxx_init(device_t dev) /* Enable the local cpu apics */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS == 1 - siblings = cpuid_ecx(0x80000008) & 0xff; + /* Find our node and core */ + id = get_node_core_id(); - id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set - - if(siblings>0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR); - msr.lo = (siblings+1)<<16; - wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1<<(33-32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - - - /* Is this a bad location? In particular can another node prefecth - * data from this node before we have initialized it? - */ - if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0 -#else - /* Is this a bad location? In particular can another node prefecth + /* Is this a bad location? In particular can another node prefetch * data from this node before we have initialized it? */ - nodeid = lapicid() & 0xf; - init_ecc_memory(nodeid); -#endif - -#if CONFIG_LOGICAL_CPUS==1 - /* Start up my cpu siblings */ -// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan -#endif + if (id.coreid == 0) { + init_ecc_memory(id.nodeid); // only do it for core 0 + } + /* Deal with sibling cpus */ + amd_sibling_init(cpu, id); } static struct device_operations cpu_dev_ops = { @@ -451,7 +414,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0xf51 }, /* SH7-B3 */ { X86_VENDOR_AMD, 0xf58 }, /* SH7-C0 */ { X86_VENDOR_AMD, 0xf48 }, -#if 1 + { X86_VENDOR_AMD, 0xf5A }, /* SH7-CG */ { X86_VENDOR_AMD, 0xf4A }, { X86_VENDOR_AMD, 0xf7A }, @@ -483,7 +446,6 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x20fc2 }, { X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 */ { X86_VENDOR_AMD, 0x20f32 }, -#endif { 0, 0 }, }; |