printk_foo -> printk(BIOS_FOO, ...)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 34 insertions, 34 deletions

diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index 23a5642867..b1d6bae7a6 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -28,21 +28,21 @@
 static void print_debug_fv(const char *str, u32 val)
 {
 #if FAM10_SET_FIDVID_DEBUG == 1
-		printk_debug("%s%x\n", str, val);
+		printk(BIOS_DEBUG, "%s%x\n", str, val);
 #endif
 }
 
 static void print_debug_fv_8(const char *str, u8 val)
 {
 #if FAM10_SET_FIDVID_DEBUG == 1
-		printk_debug("%s%02x\n", str, val);
+		printk(BIOS_DEBUG, "%s%02x\n", str, val);
 #endif
 }
 
 static void print_debug_fv_64(const char *str, u32 val, u32 val2)
 {
 #if FAM10_SET_FIDVID_DEBUG == 1
-		printk_debug("%s%x%x\n", str, val, val2);
+		printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
 #endif
 }
 
@@ -68,7 +68,7 @@ static void enable_fid_change(u8 fid)
 		dword |= (u32) fid & 0x1F;
 		dword |= 1 << 5;	// enable
 		pci_write_config32(dev, 0xd4, dword);
-		printk_debug("FID Change Node:%02x, F3xD4: %08x \n", i, dword);
+		printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, dword);
 	}
 }
 
@@ -186,7 +186,7 @@ static void prep_fid_change(void)
 	nodes = get_nodes();
 
 	for(i = 0; i < nodes; i++) {
-		printk_debug("Prep FID/VID Node:%02x \n", i);
+		printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
 		dev = NODE_PCI(i,3);
 
 		dword = pci_read_config32(dev, 0xd8);
@@ -286,15 +286,15 @@ static void prep_fid_change(void)
 		pci_write_config32(dev, 0x80, dword);
 
 		dword = pci_read_config32(dev, 0x80);
-		printk_debug("  F3x80: %08x \n", dword);
+		printk(BIOS_DEBUG, "  F3x80: %08x \n", dword);
 		dword = pci_read_config32(dev, 0x84);
-		printk_debug("  F3x84: %08x \n", dword);
+		printk(BIOS_DEBUG, "  F3x84: %08x \n", dword);
 		dword = pci_read_config32(dev, 0xD4);
-		printk_debug("  F3xD4: %08x \n", dword);
+		printk(BIOS_DEBUG, "  F3xD4: %08x \n", dword);
 		dword = pci_read_config32(dev, 0xD8);
-		printk_debug("  F3xD8: %08x \n", dword);
+		printk(BIOS_DEBUG, "  F3xD8: %08x \n", dword);
 		dword = pci_read_config32(dev, 0xDC);
-		printk_debug("  F3xDC: %08x \n", dword);
+		printk(BIOS_DEBUG, "  F3xDC: %08x \n", dword);
 
 
 	}
@@ -495,7 +495,7 @@ static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
 	u8 nodes;
 	u8 i;
 
-	printk_debug("FIDVID on AP: %02x\n", apicid);
+	printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
 
 	/* Steps 1-6 of BIOS NB COF and VID Configuration
 	 * for SVI and Single-Plane PVI Systems.
@@ -773,7 +773,7 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
 	u32 reg1fc;
 	u8 pvimode;
 
-	printk_debug("FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
+	printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
 	/* FIXME: The first half of this function is nearly the same as
 	 * init_fidvid_bsp() and the code could be combined.
 	 */
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index c43887f380..d0458dfed5 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -32,24 +32,24 @@
 
 static void print_initcpu8 (const char *strval, u8 val)
 {
-	printk_debug("%s%02x\n", strval, val);
+	printk(BIOS_DEBUG, "%s%02x\n", strval, val);
 }
 
 static void print_initcpu8_nocr (const char *strval, u8 val)
 {
-	printk_debug("%s%02x", strval, val);
+	printk(BIOS_DEBUG, "%s%02x", strval, val);
 }
 
 
 static void print_initcpu16 (const char *strval, u16 val)
 {
-	printk_debug("%s%04x\n", strval, val);
+	printk(BIOS_DEBUG, "%s%04x\n", strval, val);
 }
 
 
 static void print_initcpu(const char *strval, u32 val)
 {
-	printk_debug("%s%08x\n", strval, val);
+	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
 }
 
 
@@ -223,7 +223,7 @@ static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
 
 static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str)
 {
-		printk_debug("%s --- {	 APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
+		printk(BIOS_DEBUG, "%s --- {	 APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
 }
 
 
@@ -406,10 +406,10 @@ static u32 init_cpus(u32 cpu_init_detectedx)
 		{
 		// check warm(bios) reset to call stage2 otherwise do stage1
 			if (warm_reset_detect(id.nodeid)) {
-				printk_debug("init_fidvid_stage2 apicid: %02x\n", apicid);
+				printk(BIOS_DEBUG, "init_fidvid_stage2 apicid: %02x\n", apicid);
 				init_fidvid_stage2(apicid, id.nodeid);
 			} else {
-				printk_debug("init_fidvid_ap(stage1) apicid: %02x\n", apicid);
+				printk(BIOS_DEBUG, "init_fidvid_ap(stage1) apicid: %02x\n", apicid);
 				init_fidvid_ap(bsp_apicid, apicid, id.nodeid, id.coreid);
 			}
 		}
@@ -424,7 +424,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
 		set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
 
 		STOP_CAR_AND_CPU();
-		printk_debug("\nAP %02x should be halted but you are reading this....\n", apicid);
+		printk(BIOS_DEBUG, "\nAP %02x should be halted but you are reading this....\n", apicid);
 	}
 
 	return bsp_apicid;
@@ -449,12 +449,12 @@ static void wait_all_core0_started(void)
 	u32 i;
 	u32 nodes = get_nodes();
 
-	printk_debug("Wait all core0s started \n");
+	printk(BIOS_DEBUG, "Wait all core0s started \n");
 	for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
 		while(!is_core0_started(i)) {}
 		print_initcpu8("  Core0 started on node: ", i);
 	}
-	printk_debug("Wait all core0s started done\n");
+	printk(BIOS_DEBUG, "Wait all core0s started done\n");
 }
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 /**
@@ -471,7 +471,7 @@ static void start_node(u8 node)
 	u32 val;
 
 	/* Enable routing table */
-	printk_debug("Start node %02x", node);
+	printk(BIOS_DEBUG, "Start node %02x", node);
 
 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
 	/* For FAM10 support, we need to set Dram base/limit for the new node */
@@ -484,7 +484,7 @@ static void start_node(u8 node)
 	val &= ~(1 << 1);
 	pci_write_config32(NODE_HT(node), 0x6c, val);
 
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 }
 
 
@@ -514,7 +514,7 @@ static void setup_remote_node(u8 node)
 	};
 	u16 i;
 
-	printk_debug("setup_remote_node: %02x", node);
+	printk(BIOS_DEBUG, "setup_remote_node: %02x", node);
 
 	/* copy the default resource map from node 0 */
 	for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
@@ -525,7 +525,7 @@ static void setup_remote_node(u8 node)
 		pci_write_config32(NODE_MP(node), reg, value);
 
 	}
-	printk_debug(" done\n");
+	printk(BIOS_DEBUG, " done\n");
 }
 #endif	/* CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
@@ -845,7 +845,7 @@ void cpuSetAMDMSR(void)
 	u8 i;
 	u32 revision, platform;
 
-	printk_debug("cpuSetAMDMSR ");
+	printk(BIOS_DEBUG, "cpuSetAMDMSR ");
 
 	revision = mctGetLogicalCPUID(0xFF);
 	platform = get_platform_type();
@@ -863,7 +863,7 @@ void cpuSetAMDMSR(void)
 	}
 	AMD_Errata298();
 
-	printk_debug(" done\n");
+	printk(BIOS_DEBUG, " done\n");
 }
 
 
@@ -879,7 +879,7 @@ void cpuSetAMDPCI(u8 node)
 	u32 val;
 	u8 offset;
 
-	printk_debug("cpuSetAMDPCI %02d", node);
+	printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node);
 
 
 	revision = mctGetLogicalCPUID(node);
@@ -933,7 +933,7 @@ void cpuSetAMDPCI(u8 node)
 	if (revision & (AMD_DR_B2 | AMD_DR_B3))
 		dctPhyDiag(); */
 
-	printk_debug(" done\n");
+	printk(BIOS_DEBUG, " done\n");
 }
 
 
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 6ef1f42471..407121d2d8 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -77,7 +77,7 @@ void model_10xxx_init(device_t dev)
 #endif
 
 	id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
-	printk_debug("nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
+	printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
@@ -114,7 +114,7 @@ void model_10xxx_init(device_t dev)
 		msr.hi |= 1 << (33-32);
 		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 	}
-	printk_debug("siblings = %02d, ", siblings);
+	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
 #endif
 
 	/* DisableCf8ExtCfg */
diff --git a/src/cpu/amd/model_10xxx/processor_name.c b/src/cpu/amd/model_10xxx/processor_name.c
index 65f97765b2..29bc50802d 100644
--- a/src/cpu/amd/model_10xxx/processor_name.c
+++ b/src/cpu/amd/model_10xxx/processor_name.c
@@ -226,7 +226,7 @@ done:
 	strcpymax(&program_string[j], processor_name_string,
 		  sizeof(program_string) - j);
 
-	printk_debug("CPU model: %s\n", program_string);
+	printk(BIOS_DEBUG, "CPU model: %s\n", program_string);
 
 	for (i = 0; i < 6; i++) {
 		msr.lo = p_program_string[(2 * i) + 0];
diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c
index a24b83d42e..85b1aa84bf 100644
--- a/src/cpu/amd/model_10xxx/update_microcode.c
+++ b/src/cpu/amd/model_10xxx/update_microcode.c
@@ -97,7 +97,7 @@ void update_microcode(u32 cpu_deviceid)
 	if (equivalent_processor_rev_id != 0) {
 		amd_update_microcode((void *) microcode_updates, equivalent_processor_rev_id);
 	} else {
-		printk_debug("microcode: rev id not found. Skipping microcode patch!\n");
+		printk(BIOS_DEBUG, "microcode: rev id not found. Skipping microcode patch!\n");
 	}
 
 }