AMD Geode cpus: apply un-written naming rules

Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.

Rename directories and Kconfig as follows:
   model_lx  -> geode_lx
   model_gx1 -> geode_gx1
   model_gx2 -> geode_gx2

Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/613
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

5 files changed, 277 insertions, 0 deletions

diff --git a/src/cpu/amd/geode_gx1/Kconfig b/src/cpu/amd/geode_gx1/Kconfig
new file mode 100644
index 0000000000..4a90c26d6e
--- /dev/null
+++ b/src/cpu/amd/geode_gx1/Kconfig
@@ -0,0 +1,33 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config CPU_AMD_GEODE_GX1
+	bool
+
+if CPU_AMD_GEODE_GX1
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x01000
+
+endif # CPU_AMD_GEODE_GX1
diff --git a/src/cpu/amd/geode_gx1/Makefile.inc b/src/cpu/amd/geode_gx1/Makefile.inc
new file mode 100644
index 0000000000..d5bb1ef5ad
--- /dev/null
+++ b/src/cpu/amd/geode_gx1/Makefile.inc
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+driver-y += geode_gx1_init.c
+
+cpu_incs += $(src)/cpu/amd/geode_gx1/cpu_setup.inc
+cpu_incs += $(src)/cpu/amd/geode_gx1/gx_setup.inc
diff --git a/src/cpu/amd/geode_gx1/cpu_setup.inc b/src/cpu/amd/geode_gx1/cpu_setup.inc
new file mode 100644
index 0000000000..d701f8d226
--- /dev/null
+++ b/src/cpu/amd/geode_gx1/cpu_setup.inc
@@ -0,0 +1,68 @@
+/*
+    freebios/src/northbridge/nsc/gx1/cpu_setup.inc
+
+    Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
+
+    Initialize the GX1 CPU configuration registers
+*/
+
+/* USES: esi, ecx, eax */
+
+#include <cpu/amd/gx1def.h>
+
+	movl %eax, %ebp /* preserve bist */
+
+cpu_setup_start:
+	leal	cpu_setup_table, %esi
+	movl	$cpu_setup_len, %ecx
+
+cpu_setup_loop:
+	movw	(%esi), %ax
+	addl	$2, %esi
+	outb	%al, $0x22
+	movb	%ah, %al
+	outb	%al, $0x23
+	loop	cpu_setup_loop
+
+	movb	$0xff, %al		/* DIR1 -- Identification Register 1 */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	cmpb	$0x63, %al		/* Revision for GXLV rev 3 */
+	jbe	cpu_no_ccr4
+
+	movb	$0xe8, %al		/* CCR4 */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	orb	$0x20, %al		/* Enable FPU Fast Mode */
+	outb	%al, $0x23
+
+	movb	$0xf0, %al		/* PCR1 --- Performace Control  */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	orb	$0x02, %al		/* Incrementor on, whatever that is */
+	outb	%al, $0x23
+
+	movb	$0x20, %al		/* PCR0 --- Performace Control  */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	orb	$0x20, %al		/* Must be 1 according to data book */
+	orb	$0x04, %al		/* Incrementor Margin 10 */
+	outb	%al, $0x23
+cpu_no_ccr4:
+
+	jmp	cpu_setup_end
+
+cpu_setup_table:
+	.byte	0xc1, 0x00		/* NO SMIs */
+	.byte	0xc3, 0x14		/* Enable CPU config register */
+	.byte	0x20, 0x00
+	.byte	0xb8, GX_BASE>>30	/* Enable GXBASE address */
+	.byte	0xc2, 0x00
+	.byte	0xe8, 0x98
+	.byte	0xc3, 0xf8		/* Enable CPU config register */
+cpu_setup_len = (.-cpu_setup_table)/2
+
+cpu_setup_end:
+	nop
+
+	movl %ebp, %eax	/* Restore bist */
diff --git a/src/cpu/amd/geode_gx1/geode_gx1_init.c b/src/cpu/amd/geode_gx1/geode_gx1_init.c
new file mode 100644
index 0000000000..60f9473470
--- /dev/null
+++ b/src/cpu/amd/geode_gx1/geode_gx1_init.c
@@ -0,0 +1,101 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+
+#if 0
+#include <cpu/amd/gx1def.h>
+#include <arch/io.h>
+
+static void gx1_cpu_setup(void)
+{
+	unsigned char rreg;
+	unsigned char cpu_table[] = {
+		0xc1, 0x00,		/* NO SMIs */
+		0xc3, 0x14,		/* Enable CPU config register */
+		0x20, 0x00,		/* */
+		0xb8, GX_BASE>>30,	/* Enable GXBASE address */
+		0xc2, 0x00,
+		0xe8, 0x98,
+		0xc3, 0xf8,		/* Enable CPU config register */
+		0x00, 0x00
+		};
+	unsigned char *cPtr = cpu_table;
+
+	while(rreg = *cPtr++) {
+		unsigned char rval = *cPtr++;
+		outb(rreg, 0x22);
+		outb(rval, 0x23);
+		}
+
+	outb(0xff, 0x22);		/* DIR1 -- Identification register 1 */
+	if(inb(0x23) > 0x63) {		/* Rev greater than R3 */
+		outb(0xe8, 0x22);
+		outb(inb(0x23) | 0x20, 0x23);	/* Enable FPU Fast Mode */
+
+		outb(0xf0, 0x22);
+		outb(inb(0x23) | 0x02, 0x23);	/* Incrementor on */
+
+		outb(0x20, 0x22);
+		outb(inb(0x23) | 0x24, 0x23);	/* Bit 5 must be on */
+						/* Bit 2 Incrementor margin 10 */
+
+	}
+}
+
+static void gx1_gx_setup(void)
+{
+unsigned long gx_setup_table[] = {
+	GX_BASE + DC_UNLOCK, 		DC_UNLOCK_MAGIC,
+	GX_BASE + DC_GENERAL_CFG, 		0,
+	GX_BASE + DC_UNLOCK, 		0,
+	GX_BASE + BC_DRAM_TOP, 		0x3fffffff,
+	GX_BASE + BC_XMAP_1, 		0x60,
+	GX_BASE + BC_XMAP_2, 		0,
+	GX_BASE + BC_XMAP_3, 		0,
+	GX_BASE + MC_BANK_CFG, 		0x00700070,
+	GX_BASE + MC_MEM_CNTRL1, 	XBUSARB,
+	GX_BASE + MC_GBASE_ADD, 	0xff,
+	0, 				0
+	};
+
+unsigned long *gxPtr = gx_setup_table;
+unsigned long *gxdPtr;
+unsigned long addr;
+
+	while(addr = *gxPtr++) {
+		gxdPtr = (unsigned long *)addr;
+		*gxdPtr = *gxPtr++;
+	}
+}
+#endif
+
+static void geode_gx1_init(device_t dev)
+{
+#if 0
+	gx1_cpu_setup();
+	gx1_gx_setup();
+#endif
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+};
+
+static struct device_operations cpu_dev_ops = {
+	.init	= geode_gx1_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_CYRIX, 0x0540 },
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops	  = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
diff --git a/src/cpu/amd/geode_gx1/gx_setup.inc b/src/cpu/amd/geode_gx1/gx_setup.inc
new file mode 100644
index 0000000000..6d0e289120
--- /dev/null
+++ b/src/cpu/amd/geode_gx1/gx_setup.inc
@@ -0,0 +1,47 @@
+/*
+    freebios/src/northbridge/nsc/gx1/gx_setup.inc
+
+    Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
+
+    Setup the GX_BASE registers on a National Semiconductor Geode CPU
+*/
+
+#include <cpu/amd/gx1def.h>
+
+	movl %eax, %ebp /* Preserve bist */
+
+gx_setup_start:
+	leal	gx_setup_table, %esi
+	movl	$gx_setup_len, %ecx
+	movl	$GX_BASE, %edi
+
+gx_setup_loop:
+	movw	(%esi), %di		/* Only read the low word of address */
+	addl	$4, %esi
+	movl	(%esi), %eax		/* Data */
+	addl	$4, %esi
+	movl	%eax, (%edi)
+	loop	gx_setup_loop
+
+	jmp	gx_setup_end
+
+gx_setup_table:
+	/* Allow writes to config registers */
+	.long	DC_UNLOCK, DC_UNLOCK_MAGIC
+	.long	DC_GENERAL_CFG, 0
+	.long	DC_UNLOCK, 0
+
+	.long	BC_DRAM_TOP, 0x3fffffff
+	.long	BC_XMAP_1, 0x60
+	.long	BC_XMAP_2, 0
+	.long	BC_XMAP_3, 0
+
+	.long	MC_BANK_CFG, 0x00700070	/* No DIMMS installed */
+	.long	MC_MEM_CNTRL1, XBUSARB
+	.long	MC_GBASE_ADD, 0x7ff	/* Almost 1GB */
+gx_setup_len = (.-gx_setup_table)/8
+
+gx_setup_end:
+	nop
+
+	movl %ebp, %eax	/* Restore bist */