diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/cpu/amd/family_10h-family_15h/powernow_acpi.c | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/cpu/amd/family_10h-family_15h/powernow_acpi.c')
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/powernow_acpi.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c index 35f7952022..61da88cc49 100644 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <option.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <arch/acpigen.h> #include <cpu/amd/powernow.h> #include <device/pci.h> @@ -111,7 +112,7 @@ static void write_cstates_for_core(int coreID) cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO; cstate.resource.bit_width = 8; cstate.resource.bit_offset = 0; - cstate.resource.addrl = rdmsr(0xc0010073).lo + 1; + cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo + 1; cstate.resource.addrh = 0; cstate.resource.resv = 1; } else { @@ -121,7 +122,7 @@ static void write_cstates_for_core(int coreID) cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO; cstate.resource.bit_width = 8; cstate.resource.bit_offset = 0; - cstate.resource.addrl = rdmsr(0xc0010073).lo; + cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo; cstate.resource.addrh = 0; cstate.resource.resv = 1; } @@ -268,7 +269,8 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) if (fam15h) /* Set P_LVL2 P_BLK entry */ - *(((uint8_t *)pcontrol_blk) + 0x04) = (rdmsr(0xc0010073).lo + 1) & 0xff; + *(((uint8_t *)pcontrol_blk) + 0x04) = + (rdmsr(MSR_CSTATE_ADDRESS).lo + 1) & 0xff; uint8_t pviModeFlag; uint8_t Pstate_max; @@ -296,15 +298,15 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) pviModeFlag = 0; /* Get PSmax's index */ - msr = rdmsr(0xC0010061); + msr = rdmsr(PS_LIM_REG); Pstate_max = (uint8_t) ((msr.lo >> PS_MAX_VAL_SHFT) & ((fam15h)?BIT_MASK_7:BIT_MASK_3)); /* Determine if all enabled Pstates have the same fidvid */ uint8_t i; - uint8_t cpufid_prev = (rdmsr(0xC0010064).lo & 0x3f); + uint8_t cpufid_prev = (rdmsr(PSTATE_0_MSR).lo & 0x3f); uint8_t all_enabled_cores_have_same_cpufid = 1; for (i = 1; i < Pstate_max; i++) { - cpufid = rdmsr(0xC0010064 + i).lo & 0x3f; + cpufid = rdmsr(PSTATE_0_MSR + i).lo & 0x3f; if (cpufid != cpufid_prev) { all_enabled_cores_have_same_cpufid = 0; break; @@ -318,7 +320,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) /* Populate tables with all Pstate information */ for (Pstate_num = 0; Pstate_num < Pstate_max; Pstate_num++) { /* Get power state information */ - msr = rdmsr(0xC0010064 + Pstate_num + boost_count); + msr = rdmsr(PSTATE_0_MSR + Pstate_num + boost_count); cpufid = (msr.lo & 0x3f); cpudid = (msr.lo & 0x1c0) >> 6; cpuvid = (msr.lo & 0xfe00) >> 9; |