diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-11-24 14:11:47 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-24 23:22:34 +0100 |
| commit | 39495bae5fa5e8c72099ef585110e011d9d7696f (patch) | |
| tree | a0f8fb408e2e3c1e4169a183ea43b7fbe03b79b8 /src/cpu/amd/family_10h-family_15h/init_cpus.c | |
| parent | 6aa6eab98b37ae2d8878b2eb90c64478ab172b42 (diff) | |
cpu/amd/family_10h-family_15h: Set LDT tristate correctly on C32 sockets
The existing code unconditionally cleared the LDT tristate enable bit,
which was incorrect for C32 sockets. Update the code to be in line
with the BKDG recommendations.
Change-Id: I8095931973ea10f1467a6621092e88c6c494565a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13142
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/amd/family_10h-family_15h/init_cpus.c')
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/init_cpus.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index bf1862b7e9..1794072a64 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -1095,6 +1095,45 @@ static void cpuSetAMDPCI(u8 node) } } + if (is_fam15h()) { + if (CONFIG_CPU_SOCKET_TYPE == 0x14) { + /* Socket C32 */ + dword = pci_read_config32(NODE_PCI(node, 0), 0x84); + dword |= 0x1 << 13; /* LdtStopTriEn = 1 */ + pci_write_config32(NODE_PCI(node, 0), 0x84, dword); + + dword = pci_read_config32(NODE_PCI(node, 0), 0xa4); + dword |= 0x1 << 13; /* LdtStopTriEn = 1 */ + pci_write_config32(NODE_PCI(node, 0), 0xa4, dword); + + dword = pci_read_config32(NODE_PCI(node, 0), 0xc4); + dword |= 0x1 << 13; /* LdtStopTriEn = 1 */ + pci_write_config32(NODE_PCI(node, 0), 0xc4, dword); + + dword = pci_read_config32(NODE_PCI(node, 0), 0xe4); + dword |= 0x1 << 13; /* LdtStopTriEn = 1 */ + pci_write_config32(NODE_PCI(node, 0), 0xe4, dword); + } + else { + /* Other socket (G34, etc.) */ + dword = pci_read_config32(NODE_PCI(node, 0), 0x84); + dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */ + pci_write_config32(NODE_PCI(node, 0), 0x84, dword); + + dword = pci_read_config32(NODE_PCI(node, 0), 0xa4); + dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */ + pci_write_config32(NODE_PCI(node, 0), 0xa4, dword); + + dword = pci_read_config32(NODE_PCI(node, 0), 0xc4); + dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */ + pci_write_config32(NODE_PCI(node, 0), 0xc4, dword); + + dword = pci_read_config32(NODE_PCI(node, 0), 0xe4); + dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */ + pci_write_config32(NODE_PCI(node, 0), 0xe4, dword); + } + } + #ifdef DEBUG_HT_SETUP /* Dump link settings */ for (i = 0; i < 4; i++) { |