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author | Patrick Rudolph <siro@das-labor.org> | 2016-11-11 19:17:56 +0100 |
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committer | Patrick Rudolph <siro@das-labor.org> | 2016-11-20 14:59:59 +0100 |
commit | bec669685cdd77e12cdf8fad2e68d39218cfdba7 (patch) | |
tree | 497874d9ba7d28ad87b6899f159dfcda4e81798c /src/cpu/amd/agesa | |
parent | 78c5f0cc029ab877ab5bf018abed18684c038602 (diff) |
nb/intel/sandybridge/raminit: Fix CAS Write Latency
As documented in DDR3 spec for MR2 the CWL is based on DDR frequency.
There's no to little difference for most memory modules operating at DDR3-1333.
It might fix problems for memory modules that operate at a higher frequency and
memory modules with low CL values should work even better.
Tested on Lenovo T420 with DDR3-1333 CL9 and DDR3-1600 CL11.
No regressions found.
Change-Id: Ib90b5de872a219cf80b4976b6dfae6bc02e298f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17389
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/amd/agesa')
0 files changed, 0 insertions, 0 deletions