diff options
| author | Naresh G Solanki <naresh.solanki@intel.com> | 2017-03-16 15:30:25 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-07 21:44:29 +0200 |
| commit | fb7937918ae4c52c2c6b9749e3cd3277615e2f6e (patch) | |
| tree | 94b59e6dbbe5cbdff772dfa7b85ec70b1ebb4be4 /src/cpu/amd/agesa/family15tn/acpi | |
| parent | 44ff10eaa6f480067b080138ced567122cb2a000 (diff) | |
soc/intel/skylake: Enable XHCI clock gate control in ACPI
Enable SS link trunk clock gating & D3hot when device enters
D3 state.
Similarly disable SS link trunk clock gating & D3hot when device enters
D0 state
TEST=Build & boot Poppy board. Check working for XHCI wake when DUT
is in S3.
Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18879
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/agesa/family15tn/acpi')
0 files changed, 0 insertions, 0 deletions