diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/cpu/amd/agesa/family14 | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/cpu/amd/agesa/family14')
| -rw-r--r-- | src/cpu/amd/agesa/family14/fixme.c | 6 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/family14/model_14_init.c | 12 |
2 files changed, 7 insertions, 11 deletions
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 7d595853e6..33e164354e 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -14,7 +14,7 @@ */ #include <cpu/x86/mtrr.h> - +#include <cpu/amd/msr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <AGESA.h> #include "amdlib.h" @@ -78,7 +78,7 @@ void amd_initmmio(void) Address MSR register. */ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); /* Set Ontario Link Data */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); @@ -96,7 +96,7 @@ void amd_initmmio(void) /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ MsrReg = 0; - LibAmdMsrWrite (0xC0010062, &MsrReg, &StdHeader); + LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader); } void amd_initenv(void) diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index b49d975761..3f0501e5cb 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -15,6 +15,8 @@ #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <device/device.h> #include <string.h> @@ -23,15 +25,9 @@ #include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/amdfam14.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/agesa_helper.h> -#define MCG_CAP 0x179 -# define MCA_BANKS_MASK 0xff -#define MC0_STATUS 0x401 - static void model_14_init(struct device *dev) { u8 i; @@ -78,12 +74,12 @@ static void model_14_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); |