diff options
author | Patrick Georgi <patrick.georgi@secunet.com> | 2012-11-20 11:53:47 +0100 |
---|---|---|
committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-27 23:51:52 +0100 |
commit | e135ac5a7ea69b6edcb89345019212f5de412b1e (patch) | |
tree | 408611a9f2846867f9731af53b1f08dd32eb6851 /src/cpu/amd/agesa/Kconfig | |
parent | bdc1816b2379bdf569ac6746172bba41e1307917 (diff) |
Remove AMD special case for LAPIC based udelay()
- Optionally override FSB clock detection in generic
LAPIC code with constant value.
- Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz
- compile LAPIC code for romstage, too
- Remove #include ".../apic_timer.c" in AMD based mainboards
- Remove custom udelay implementation from intel northbridges' romstages
Future work:
- remove the compile time special case
(requires some cpuid based switching)
- drop northbridge udelay implementations (i945, i5000) if
not required anymore (eg. can SMM use the LAPIC timer?)
Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1618
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/agesa/Kconfig')
-rw-r--r-- | src/cpu/amd/agesa/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 39175fc79e..d57bded604 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,6 +26,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_TN default n select TSC_SYNC_LFENCE + select UDELAY_LAPIC if CPU_AMD_AGESA @@ -44,6 +45,10 @@ config XIP_ROM_SIZE In order to execute romstage in place on the flash rom, more space is required to be set as write through caching. +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig |