From e135ac5a7ea69b6edcb89345019212f5de412b1e Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 20 Nov 2012 11:53:47 +0100 Subject: Remove AMD special case for LAPIC based udelay() - Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer Tested-by: Stefan Reinauer --- src/cpu/amd/agesa/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/cpu/amd/agesa/Kconfig') diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 39175fc79e..d57bded604 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,6 +26,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_TN default n select TSC_SYNC_LFENCE + select UDELAY_LAPIC if CPU_AMD_AGESA @@ -44,6 +45,10 @@ config XIP_ROM_SIZE In order to execute romstage in place on the flash rom, more space is required to be set as write through caching. +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig -- cgit v1.2.3