cpu/allwinner/a10: Add function for reading chip revision

Change-Id: Iafbd253235db3914b9382fdb41de2622ef83c6d8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4596
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>

2 files changed, 20 insertions, 0 deletions

diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c
index 60cc60c4d1..7d5d1419c3 100644
--- a/src/cpu/allwinner/a10/timer.c
+++ b/src/cpu/allwinner/a10/timer.c
@@ -11,6 +11,7 @@
 #include <delay.h>
 #include <timer.h>
 
+struct a1x_timer_module *const timer_module = (void *)A1X_TIMER_BASE;
 struct a1x_timer *const tmr0 =
 		&((struct a1x_timer_module *)A1X_TIMER_BASE)->timer[0];
 
@@ -53,3 +54,13 @@ void udelay(unsigned usec)
 	}
 
 }
+
+/*
+ * This function has nothing to do with timers; however, the chip revision
+ * register is in the timer module, so keep this function here.
+ */
+u8 a1x_get_cpu_chip_revision(void)
+{
+	write32(0, &timer_module->cpu_cfg);
+	return (read32(&timer_module->cpu_cfg) >> 6) & 0x3;
+}
diff --git a/src/cpu/allwinner/a10/timer.h b/src/cpu/allwinner/a10/timer.h
index 9c0c0d158d..cb127530a1 100644
--- a/src/cpu/allwinner/a10/timer.h
+++ b/src/cpu/allwinner/a10/timer.h
@@ -24,6 +24,13 @@
 #define TIMER_CTRL_RELOAD		(1 << 1)
 #define TIMER_CTRL_TMR_EN		(1 << 0)
 
+/* Chip revision definitions (found in CPU_CFG register) */
+#define A1X_CHIP_REV_A			0x0
+#define A1X_CHIP_REV_C1			0x1
+#define A1X_CHIP_REV_C2			0x2
+#define A1X_CHIP_REV_B			0x3
+
+
 /* General purpose timer */
 struct a1x_timer {
 	u32 ctrl;
@@ -87,4 +94,6 @@ struct a1x_timer_module {
 	u32 cpu_cfg;
 } __attribute__ ((packed));
 
+u8 a1x_get_cpu_chip_revision(void);
+
 #endif				/* CPU_ALLWINNER_A10_TIMER_H */