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authorJulius Werner <jwerner@chromium.org>2015-02-19 14:51:15 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:22:28 +0200
commit2f37bd65518865688b9234afce0d467508d6f465 (patch)
treeeba5ed799de966299602b30c70d51dd40eaadd73 /src/cpu/allwinner/a10/twi.c
parent1f60f971fc89ef841e81b978964b38278d597b1d (diff)
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/allwinner/a10/twi.c')
-rw-r--r--src/cpu/allwinner/a10/twi.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c
index b5d9880847..f780721e10 100644
--- a/src/cpu/allwinner/a10/twi.c
+++ b/src/cpu/allwinner/a10/twi.c
@@ -42,7 +42,7 @@ static void configure_clock(struct a1x_twi *twi, u32 speed_hz)
/* Pre-divide the clock by 8 */
n = 3;
m = (apb_clk >> n) / speed_hz;
- writel(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk);
+ write32(&twi->clk, TWI_CLK_M(m) | TWI_CLK_N(n));
}
void a1x_twi_init(u8 bus, u32 speed_hz)
@@ -53,9 +53,9 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
configure_clock(twi, speed_hz);
/* Enable the I²C bus */
- writel(TWI_CTL_BUS_EN, &twi->ctl);
+ write32(&twi->ctl, TWI_CTL_BUS_EN);
/* Issue soft reset */
- writel(1, &twi->reset);
+ write32(&twi->reset, 1);
while (i-- && read32(&twi->reset))
udelay(1);
@@ -63,12 +63,12 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
static void clear_interrupt_flag(struct a1x_twi *twi)
{
- writel(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl);
+ write32(&twi->ctl, read32(&twi->ctl) & ~TWI_CTL_INT_FLAG);
}
static void i2c_send_data(struct a1x_twi *twi, u8 data)
{
- writel(data, &twi->data);
+ write32(&twi->data, data);
clear_interrupt_flag(twi);
}
@@ -90,7 +90,7 @@ static void i2c_send_start(struct a1x_twi *twi)
reg32 = read32(&twi->ctl);
reg32 &= ~TWI_CTL_INT_FLAG;
reg32 |= TWI_CTL_M_START;
- writel(reg32, &twi->ctl);
+ write32(&twi->ctl, reg32);
/* M_START is automatically cleared after condition is transmitted */
i = TWI_TIMEOUT;
@@ -106,7 +106,7 @@ static void i2c_send_stop(struct a1x_twi *twi)
reg32 = read32(&twi->ctl);
reg32 &= ~TWI_CTL_INT_FLAG;
reg32 |= TWI_CTL_M_STOP;
- writel(reg32, &twi->ctl);
+ write32(&twi->ctl, reg32);
}
static int i2c_read(struct a1x_twi *twi, uint8_t chip,