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authorMartin Roth <gaumless@gmail.com>2022-10-17 13:52:19 -0600
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-10-25 17:15:58 +0000
commit771806da4996ab6f1b6a920bbf9ba21fb9e45474 (patch)
tree3dd1d8c951cecb8825a5637cfed484c27946469d /src/console
parentf6fea4fd075a82b9ed66515f98e646c5d59d6a58 (diff)
console: Add an SoC-specific post-code call
Add a post-code call that SoCs can hook to output or save in any way that is specific to that SoC. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/console')
-rw-r--r--src/console/post.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/console/post.c b/src/console/post.c
index 1d99a2e9dd..35e87799a8 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -5,6 +5,7 @@
/* Write POST information */
void __weak arch_post_code(uint8_t value) { }
+void __weak soc_post_code(uint8_t value) { }
/* Some mainboards have very nice features beyond just a simple display.
* They can override this function.
@@ -18,6 +19,8 @@ void post_code(uint8_t value)
for displaying POST so keep it first. */
arch_post_code(value);
+ soc_post_code(value);
+
if (CONFIG(CONSOLE_POST))
printk(BIOS_INFO, "POST: 0x%02x\n", value);