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| author | Husni Faiz <ahamedhusni73@gmail.com> | 2022-09-05 15:23:15 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-09-16 17:01:17 +0000 |
| commit | 67300f88cd1e950ca18c4e7bdd770ef18b8c06dd (patch) | |
| tree | 7f3ede354ef995eba43628e5681d84369f4a958d /src/console | |
| parent | c5d0761dea84b28cd5993b8775a4559974cc8c04 (diff) | |
drivers/smbus: add smbus console driver
This patch adds a new smbus console driver and Kconfig
options to enable the driver.
Change-Id: Ife77fb2c3e1cc77678a4972701317d50624ceb95
Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67339
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/console')
| -rw-r--r-- | src/console/Kconfig | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/console/Kconfig b/src/console/Kconfig index 479b7f567e..9b8e9f87c8 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -297,6 +297,30 @@ config CONSOLE_SPI_FLASH_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. +config CONSOLE_I2C_SMBUS + bool "SMBus console output" + depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS + help + Send coreboot debug output to the SMBus. + The output can be read with an I2C slave device connected + the SMBus. Please refer to the technotes section of the + coreboot documentation for more details. + +if CONSOLE_I2C_SMBUS + comment "Set logging device address and data register address" + +config CONSOLE_I2C_SMBUS_SLAVE_ADDRESS + hex "I2C slave address of the logging device" + help + I2C address of the device which logs the data. + +config CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER + hex "Data register address of the I2C logging device" + help + This an 8-bit data register. + +endif # CONSOLE_I2C_SMBUS + config CONSOLE_QEMU_DEBUGCON bool "QEMU debug console output" depends on CPU_QEMU_X86 |