summaryrefslogtreecommitdiff
path: root/src/console/post.c
diff options
context:
space:
mode:
authorXiang Wang <wxjstz@126.com>2018-08-29 17:21:19 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-09-05 10:04:57 +0000
commit21ed107958b3a2525f01875162d5a83a7900d4b4 (patch)
treea598872bb0270788b51f748f7f5bc3e3e8abf282 /src/console/post.c
parent384e9aed8c477922c960e2cbd429bd3a15b371de (diff)
riscv: add entry assembly file for RAMSTAGE
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this. Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/console/post.c')
0 files changed, 0 insertions, 0 deletions