soc/intel/tigerlake: update elog to include CSME reset causes

Call out the CSME-initiated bits from HPR_CAUSE0 register and
update the elog to include reset causes

Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14
Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

0 files changed, 0 insertions, 0 deletions