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authorNico Huber <nico.huber@secunet.com>2016-10-05 17:46:49 +0200
committerNico Huber <nico.h@gmx.de>2016-11-29 23:45:40 +0100
commitc83239eabc3b09273294a013c4dcb84f09ab0241 (patch)
tree6d3eacf46f8e5a7c5add0c58229093f7fd269520 /src/console/Kconfig
parent079b5c65c3347d2539a6b3d7d88a194f2d66ad40 (diff)
Hook up libhwbase in ramstage
It's hidden behind a configuration option `CONFIG_RAMSTAGE_LIBHWBASE`. This also adds some glue code to use the coreboot console for debug output and our monotonic timer framework as timer backend. v2: Also update 3rdparty/libhwbase to the latest master commit. Change-Id: I8e8d50271b46aac1141f95ab55ad323ac0889a8d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/console/Kconfig')
-rw-r--r--src/console/Kconfig9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 8f74613847..caf91ab252 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -399,4 +399,13 @@ config NO_EARLY_BOOTBLOCK_POSTCODES
POST codes that go out before the chipset's bootblock initialization
can happen. This option suppresses those POST codes.
+config HWBASE_DEBUG_CB
+ bool
+ default y if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+ default n
+
+config HWBASE_DEBUG_NULL
+ def_bool y
+ depends on !HWBASE_DEBUG_CB
+
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