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authorYinghai Lu <yinghailu@gmail.com>2006-04-03 20:38:34 +0000
committerYinghai Lu <yinghailu@gmail.com>2006-04-03 20:38:34 +0000
commit9a791dffeae2097aa0a18f645ce07acfed41b9bc (patch)
tree2d0359536fe3c1a0c313440b6be4ed09397dade9 /src/config
parentffb7d8a31ae899f611235cd0a7f3579d34cd8cde (diff)
new cache_as_ram support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/config')
-rw-r--r--src/config/Options.lb12
1 files changed, 9 insertions, 3 deletions
diff --git a/src/config/Options.lb b/src/config/Options.lb
index b5569673d7..1342366fe9 100644
--- a/src/config/Options.lb
+++ b/src/config/Options.lb
@@ -280,11 +280,17 @@ define DCACHE_RAM_BASE
comment "Base address of data cache when using it for temporary RAM"
end
define DCACHE_RAM_SIZE
- default none
+ default 0x1000
format "0x%x"
- export used
+ export always
comment "Size of data cache when using it for temporary RAM"
end
+define DCACHE_RAM_GLOBAL_VAR_SIZE
+ default 0
+ format "0x%x"
+ export always
+ comment "Size of region that for global variable of cache as ram stage"
+end
define XIP_ROM_BASE
default 0
format "0x%x"
@@ -310,7 +316,7 @@ define CONFIG_UNCOMPRESSED
end
define CONFIG_LB_MEM_TOPK
format "%d"
- default 1024
+ default 2048
export always
comment "Kilobytes of memory to initialized before executing code from RAM"
end