diff options
author | Julius Werner <jwerner@chromium.org> | 2017-12-14 18:12:56 -0800 |
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committer | Martin Roth <martinroth@google.com> | 2017-12-20 16:43:56 +0000 |
commit | 621b022c3b0a0aaa93fa45e889472ded5a2a4557 (patch) | |
tree | 7a56375789900571f355904d847d0ceee05baa23 /src/commonlib/mem_pool.c | |
parent | 916fc80b69a5273fd9c8ddb1a2dd403840ce6af2 (diff) |
google/gru: Adjust to incorrect strapping resistors on Kevin
It seems that RAM code 0 has been strapped with an incorrect resistor on
Kevin. The resulting voltage divide still puts it well within the ADC
value bucket reserved for that slot, but a little closer to the edge
than necessary. While this doesn't seem to cause any immediate problems
on its own, it still doesn't hurt to fix it (if only for the
documentation value).
On other boards (at least on my Scarlet) the strapping seems to be
correct.
Change-Id: Ic5199834fbeaf734e725ff45b04f45eefe149855
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22891
Reviewed-by: David Schneider <dnschneid@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/commonlib/mem_pool.c')
0 files changed, 0 insertions, 0 deletions