diff options
| author | Julius Werner <jwerner@chromium.org> | 2016-01-20 18:01:15 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-27 16:27:18 +0100 |
| commit | 4f7a3614cd07acdb6855c32eea38e5585834ee24 (patch) | |
| tree | a833e29b193ef0d6467a9d0162226762f0601c90 /src/commonlib/include | |
| parent | 95bfcaecf9c054bd116b7f36339f8de595026f28 (diff) | |
chromeos: Add timestamps to measure VPD read times
This patch adds three timestamps to coreboot and the cbmem utility that
track the time required to read in the Chrome OS Vital Product Data
(VPD) blocks (RO and RW). It's useful to account for these like all
other large flash accesses, since their size is variable.
BRANCH=None
BUG=None
TEST=Booted Oak, found my weird 100ms gap at the start of ramstage
properly accounted for.
Change-Id: I2024ed4f7d5e5ae81df9ab5293547cb5a10ff5e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b97288b5ac67ada56e2ee7b181b28341d54b7234
Original-Change-Id: Ie69c1a4ddb6bd3f1094b3880201d53f1b5373aef
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322831
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/commonlib/include')
| -rw-r--r-- | src/commonlib/include/commonlib/timestamp_serialized.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index f7c91c7448..6ce087924d 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -69,6 +69,9 @@ enum timestamp_id { TS_DONE_LOADING = 508, TS_DONE_HASHING = 509, TS_END_HASH_BODY = 510, + TS_START_COPYVPD = 550, + TS_END_COPYVPD_RO = 551, + TS_END_COPYVPD_RW = 552, /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ TS_FSP_MEMORY_INIT_START = 950, |