diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2022-01-14 17:00:45 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-21 22:43:30 +0000 |
| commit | 1587324a0dbcb9e3222aec6356de574dcc631747 (patch) | |
| tree | 900fb32e02c9da437095c3e369b6c90d628c1b96 /src/commonlib/include | |
| parent | e383b3dcc4650f81de4a20735d8a37b0720377f6 (diff) | |
commonlib: Add new "CSME ROM started execution" TS
BUG=b:182575295
TEST=Boot to OS, check cbmem -t
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 80,408
945:CSE started to handle ICC configuration 80,408 (0)
946:CSE sent 'Host BIOS Prep Done' to PMC 82,408 (2,000)
947:CSE received 'CPU Reset Done Ack sent' from PMC 242,408 (160,000)
0:1st timestamp 331,797 (89,389)
11:start of bootblock 359,484 (27,686)
12:end of bootblock 377,417 (17,932)
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9e4ccd0b8c301e4eec1a09ee8919a577ade938ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/commonlib/include')
| -rw-r--r-- | src/commonlib/include/commonlib/timestamp_serialized.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 5c5e56b071..492508ef40 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -122,7 +122,7 @@ enum timestamp_id { TS_START_CSE_FW_SYNC = 948, TS_END_CSE_FW_SYNC = 949, - /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ + /* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */ TS_FSP_MEMORY_INIT_START = 950, TS_FSP_MEMORY_INIT_END = 951, TS_FSP_TEMP_RAM_EXIT_START = 952, @@ -140,6 +140,9 @@ enum timestamp_id { TS_FSP_MEMORY_INIT_LOAD = 970, TS_FSP_SILICON_INIT_LOAD = 971, + /* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */ + TS_ME_ROM_START = 990, + /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */ /* Depthcharge entry IDs start at 1000 */ @@ -283,6 +286,7 @@ static const struct timestamp_id_to_name { { TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"}, { TS_START_CSE_FW_SYNC, "starting CSE firmware sync"}, { TS_END_CSE_FW_SYNC, "finished CSE firmware sync"}, + { TS_ME_ROM_START, "CSME ROM started execution"}, /* FSP related timestamps */ { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" }, |