diff options
| author | Reka Norman <rekanorman@google.com> | 2022-09-13 14:06:52 +1000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-06 21:16:24 +0000 |
| commit | 7b5a93153a17b728031e9a5351b6fb0176aa3a37 (patch) | |
| tree | cd989ba3daacc7bee07638b4c81ace21b922d4e8 /src/commonlib/bsd | |
| parent | c4fbeacd01772ad297d5c508bc44e9fa3bc27fb6 (diff) | |
drivers/intel/fsp2_0: Update MRC cache in ramstage
Currently the MRC cache is updated in romstage, immediately after
returning from FSP-M. Since cbmem is not cached in romstage, the update
is slow (~6 ms on nissa). Specifically, the new MRC data returned by the
FSP is stored in the FSP reserved memory in cbmem, so hashing the new
data is slow.
Move the MRC cache update to ramstage, where cbmem is cached. On nissa,
this saves ~5 ms of boot time.
Before:
552:finished loading ChromeOS VPD (RW) 631,667 (16)
3:after RAM initialization 637,703 (6,036)
4:end of romstage 650,307 (12,603)
After:
552:finished loading ChromeOS VPD (RW) 631,832 (15)
3:after RAM initialization 633,002 (1,169)
4:end of romstage 645,582 (12,580)
In ramstage, save_mrc_data() takes ~138 us.
BUG=b:242667207
TEST=MRC caching still works as expected on nivviks - after clearing the
MRC cache, memory is retrained on the next boot, but cached data is used
on subsequent boots.
Change-Id: Ie6aa2dee83a3ab8913830746593935d36a034b8d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/commonlib/bsd')
| -rw-r--r-- | src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index 1e63c6622c..d0feb39af9 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -26,6 +26,7 @@ #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052 #define CBMEM_ID_FSP_RUNTIME 0x52505346 +#define CBMEM_ID_FSPM_VERSION 0x56505346 #define CBMEM_ID_GDT 0x4c474454 #define CBMEM_ID_HOB_POINTER 0x484f4221 #define CBMEM_ID_IGD_OPREGION 0x4f444749 @@ -108,6 +109,7 @@ { CBMEM_ID_FREESPACE, "FREE SPACE " }, \ { CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \ { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \ + { CBMEM_ID_FSPM_VERSION, "FSPM VERSION" }, \ { CBMEM_ID_GDT, "GDT " }, \ { CBMEM_ID_HOB_POINTER, "HOB " }, \ { CBMEM_ID_IGD_OPREGION, "IGD OPREGION" }, \ |