diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-01 17:16:06 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-01 17:16:06 +0000 |
| commit | 9d24c7f202c4ff353a8a97e955ee68ed340a98b1 (patch) | |
| tree | af95887035012a8703fbcfbd0db03603e0474ad4 /src/arch | |
| parent | d3b2bbe08c59e36488ca9d04d01ddd61c04504ca (diff) | |
- Simplify stack size determination: MAX_CPUS * STACK_SIZE
- Check that this doesn't run into vga/oprom/bios area at link time
- Avoid overly complicated and not well understood hack which avoids that
area by leaving a hole in the stack area.
- Adapt technexion/tim5690 to put ramstage at 1MB
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/i386/coreboot_ram.ld | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/i386/coreboot_ram.ld b/src/arch/i386/coreboot_ram.ld index 2b603ea796..3915f31fd0 100644 --- a/src/arch/i386/coreboot_ram.ld +++ b/src/arch/i386/coreboot_ram.ld @@ -100,11 +100,11 @@ SECTIONS _ebss = .; _end = .; . = ALIGN(CONFIG_STACK_SIZE); + _stack = .; .stack . : { /* Reserve a stack for each possible cpu */ - /* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/ - . += ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE); + . += CONFIG_MAX_CPUS*CONFIG_STACK_SIZE; } _estack = .; _heap = .; @@ -114,6 +114,10 @@ SECTIONS . = ALIGN(4); } _eheap = .; + + /* Avoid running into 0xa0000-0xfffff */ + _bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB"); + /* The ram segment * This is all address of the memory resident copy of coreboot. */ |