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authorDavid Hendricks <dhendrix@chromium.org>2012-12-27 15:23:57 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-01-03 06:41:36 +0100
commit8583ac390a23a09c4bf75b3b9a9f2294d0523d87 (patch)
treec416849dd73b66c268edb6d39f8c95c5de039c77 /src/arch
parent1e0e55615f86bb9237fa8f4d81158cbf25c65565 (diff)
armv7: create init.S for early ARMv7 init
The old start.S file did a lot of work and had AP-specific #ifndef's. The new init.S will eventually contain only bare minimum generic ARM code for use by the bootblock. Processor-specific stuff and things that take place later in the boot process should go elsewhere. Change-Id: I7db0a77ee4bbad1ddecb193ea125d8941a50532b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2083 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/armv7/Makefile.inc4
-rw-r--r--src/arch/armv7/init/init.S94
2 files changed, 95 insertions, 3 deletions
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index b413d3e0c3..1a1271f6e1 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -142,9 +142,7 @@ endif
CFLAGS += -D__KERNEL__
CFLAGS += -D__LINUX_ARM_ARCH__=7
-# FIXME(dhendrix): trying to split start.S apart...
-crt0s = $(src)/arch/armv7/start.S
-#crt0s = $(src)/arch/armv7/romstage.S
+crt0s = $(src)/arch/armv7/init/init.S
ldscripts =
ldscripts += $(src)/arch/armv7/romstage.ld
diff --git a/src/arch/armv7/init/init.S b/src/arch/armv7/init/init.S
new file mode 100644
index 0000000000..033637e89a
--- /dev/null
+++ b/src/arch/armv7/init/init.S
@@ -0,0 +1,94 @@
+/*
+ * Early initialization code for ARMv7 architecture.
+ *
+ * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
+ * U-Boot, which itself got the file from armboot.
+ *
+ * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
+ * Copyright (c) 2013 The Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define __ASSEMBLY__
+#include <system.h>
+
+.globl _start
+_start: b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt: .word _software_interrupt
+_prefetch_abort: .word _prefetch_abort
+_data_abort: .word _data_abort
+_not_used: .word _not_used
+_irq: .word _irq
+_fiq: .word _fiq
+_pad: .word 0x12345678 /* now 16*4=64 */
+
+ .balignl 16,0xdeadbeef
+
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0, cpsr
+ bic r0, r0, #0x1f
+ orr r0, r0, #0xd3
+ msr cpsr,r0
+
+ /*
+ * From Cortex-A Series Programmer's Guide:
+ * Only CPU 0 performs initialization. Other CPUs go into WFI
+ * to do this, first work out which CPU this is
+ * this code typically is run before any other initialization step
+ */
+ mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register
+ and r1, r1, #0x3 @ Extract CPU ID bits
+ cmp r1, #0
+ bne wait_for_interrupt @ If this is not core0, wait
+
+ /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
+ mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
+ bic r0, #CR_V @ V = 0
+ mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
+
+ /* Set vector address in CP15 VBAR register */
+ ldr r0, =_start
+ mcr p15, 0, r0, c12, c0, 0 @Set VBAR
+
+/* Set stackpointer in internal RAM to call board_init_f */
+call_board_init_f:
+ ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ mov sp, r0
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+ ldr r0,=0x00000000
+ bl board_init_f
+
+wait_for_interrupt:
+ wfi
+ mov pc, lr @ back to my caller