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authorAaron Durbin <adurbin@chromium.org>2016-03-02 15:26:10 -0600
committerAaron Durbin <adurbin@chromium.org>2016-03-04 04:49:46 +0100
commit8198c678f7a7b1e3fbb44190903768397951e1f9 (patch)
tree02d7d5ba952fb78c3b91abc9b90c8c98c3296830 /src/arch
parent4330a9c8e52a00bf7b0b9ddd57717b7a39123ecf (diff)
arch/x86: always use _start as entry symbol for all stages
Instead of keeping track of all the combinations of entry points depending on the stage and other options just use _start. That way, there's no need to update the arch/header.ld for complicated cases as _start is always the entry point for a stage. Change-Id: I7795a5ee1caba92ab533bdb8c3ad80294901a48b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13882 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/include/arch/header.ld23
1 files changed, 0 insertions, 23 deletions
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index d7fbf07ac4..77eb187222 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -20,27 +20,4 @@ PHDRS
to_load PT_LOAD;
}
-/*
- * For CONFIG_SEPARATE_VERSTAGE romstage doesn't have the cache-as-ram setup.
- * It only contains the teardown code. The verstage has the cache-as-ram setup
- * code. Therefore, it needs the protected_start symbol as its entry point.
- * The romstage entry will be named _start for consistency, but it's likely
- * to be implemented in the chipset code in order to control the logic flow.
- */
-#if IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)
- #if ENV_RAMSTAGE || ENV_RMODULE || ENV_ROMSTAGE
- ENTRY(_start)
- #elif ENV_VERSTAGE
- ENTRY(protected_start)
- #endif
-#else
- #if ENV_RAMSTAGE || ENV_RMODULE
- ENTRY(_start)
- #elif ENV_ROMSTAGE
- ENTRY(protected_start)
- #endif
-#endif
-
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) && ENV_BOOTBLOCK
ENTRY(_start)
-#endif