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authorXiang Wang <wxjstz@126.com>2018-07-08 10:01:14 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-09-04 12:35:47 +0000
commit3b5351d0444f028ebdb5d06ee51197e516b0c31e (patch)
tree665f382c05c786bcd965308fb3a48ee099a58994 /src/arch
parent33354ddaa8bf067b86e283814fc3f03a02b1dfe5 (diff)
riscv: add spin lock support
Add spin lock support for riscv. Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/riscv/include/arch/smp/spinlock.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h
index bdf8ec4584..dc561d30a1 100644
--- a/src/arch/riscv/include/arch/smp/spinlock.h
+++ b/src/arch/riscv/include/arch/smp/spinlock.h
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2018 HardenedLinux.
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -10,3 +12,29 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
+#ifndef ARCH_SMP_SPINLOCK_H
+#define ARCH_SMP_SPINLOCK_H
+
+#include <arch/encoding.h>
+#include <arch/smp/atomic.h>
+
+#define barrier() { asm volatile ("fence" ::: "memory"); }
+
+typedef struct {
+ volatile atomic_t lock;
+} spinlock_t;
+
+static inline void spinlock_lock(spinlock_t *lock)
+{
+ while (atomic_swap(&lock->lock, -1))
+ ;
+ barrier();
+}
+
+static inline void spinlock_unlock(spinlock_t *lock)
+{
+ barrier();
+ atomic_set(&lock->lock, 0);
+}
+
+#endif // ARCH_SMP_SPINLOCK_H