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| author | Sergii Dmytruk <sergii.dmytruk@3mdeb.com> | 2021-08-21 16:24:02 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-11 20:18:05 +0000 |
| commit | 3a96074441c4e2b28d6d6961b94fec5c4eada8ec (patch) | |
| tree | aa5d68b48b0032f538cd8fa18552ef9c4c245cd5 /src/arch | |
| parent | dba9b54731c000b26334bd31a7dbd0fa2dbe80aa (diff) | |
src/arch/ppc64/*: pass FDT address to payload
It's available in %r3 in bootblock and needs to be passed to payload in
%r27. We use one of two hypervisor's special registers as a buffer,
which aren't used for anything by the code.
Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/ppc64/bootblock_crt0.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/ppc64/bootblock_crt0.S b/src/arch/ppc64/bootblock_crt0.S index 3988583bee..5a9496024e 100644 --- a/src/arch/ppc64/bootblock_crt0.S +++ b/src/arch/ppc64/bootblock_crt0.S @@ -3,6 +3,8 @@ * Early initialization code for POWER8/POWER9. */ +#include <cpu/power/spr.h> + #define FIXUP_ENDIAN \ tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ b $+44; /* Skip trampoline if endian is good */ \ @@ -35,6 +37,10 @@ _start: nop FIXUP_ENDIAN + /* Store FDT address provided by QEMU in %r3 to pass it later to + * payload */ + mtspr SPR_HSPRG0, %r3 + /* Set program priority to medium */ or %r2, %r2, %r2 |