diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2017-09-29 01:36:58 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-11-07 12:29:27 +0000 |
| commit | 140a827daa5d878d7b34853dd2b15c64c8d501d1 (patch) | |
| tree | d65da84f9e4933518ee58af5be99e4b1c9dd06ff /src/arch | |
| parent | 92f0513a0ca8a3d262f3e16f17366a2e517fec74 (diff) | |
arch/riscv: Drop mret workaround
Our toolchain can compile mret now, and once the encoding changes, we'll
have to adjust the code anyway.
Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/riscv/payload.S | 5 | ||||
| -rw-r--r-- | src/arch/riscv/trap_util.S | 4 |
2 files changed, 3 insertions, 6 deletions
diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S index ce88bc3f64..a189adf1db 100644 --- a/src/arch/riscv/payload.S +++ b/src/arch/riscv/payload.S @@ -24,7 +24,4 @@ riscvpayload: li t2, (1<<11) or t0, t0, t2 csrw mstatus, t0 - - // We're still in toolchain no mans land. - .word 0x30200073 - //mret + mret diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index ae32379562..44cfab7c99 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -141,10 +141,10 @@ supervisor_call_return: csrr a0, mscratch restore_regs # go back into supervisor call - .word 0x30200073 # mret + mret .global machine_call_return machine_call_return: csrr a0, mscratch restore_regs # go back into machine call - .word 0x30200073 # mret + mret |