diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-04-10 16:45:39 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-04-26 10:52:21 +0000 |
| commit | ae1b2d49cf0ad09ff8f1e3904a9e7b23d6fb423b (patch) | |
| tree | 41a0e28f6df404725371c5d5c57162bd9f9653d8 /src/arch | |
| parent | ddc37d69cb29327217151bd15a906177bc7949de (diff) | |
soc/intel: Introduce ioapic_get_sci_pin()
According to ACPI Release 6.5 systems supporting PIC (i8259)
interrupt mechanism need to report IRQ vector for the SCI_INT
field. In PIC mode only IRQ0..15 are allowed hardware vectors.
This change should cover section 5.2.9 to not pass SCI_INT
larger than IRQ15. Section 5.2.15.5 needs follow-up work.
Care should be taken that ioapic_get_sci_pin() is called
after platform code has potentially changed the routing
from the default.
It appears touched all platforms except siemens/mc_aplX
currently program SCI as IRQ9.
Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86/include/arch/ioapic.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 6c5282b90d..9dc2339dec 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -22,6 +22,8 @@ void register_new_ioapic(void *ioapic_base); void register_new_ioapic_gsi0(void *ioapic_base); void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags); #endif #endif |