From ae1b2d49cf0ad09ff8f1e3904a9e7b23d6fb423b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 10 Apr 2023 16:45:39 +0300 Subject: soc/intel: Introduce ioapic_get_sci_pin() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. Care should be taken that ioapic_get_sci_pin() is called after platform code has potentially changed the routing from the default. It appears touched all platforms except siemens/mc_aplX currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Arthur Heymans --- src/arch/x86/include/arch/ioapic.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/arch') diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 6c5282b90d..9dc2339dec 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -22,6 +22,8 @@ void register_new_ioapic(void *ioapic_base); void register_new_ioapic_gsi0(void *ioapic_base); void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags); #endif #endif -- cgit v1.2.3