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authorLee Leahy <leroy.p.leahy@intel.com>2016-06-08 07:11:48 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-06-09 17:42:12 +0200
commit3892597349cdbdf5378718ceb03dbbc53f5d543a (patch)
tree400d75aeff7e5c560b591be27624c2c0f8fef1eb /src/arch/x86
parent538b324c5f6e890b435dd88f4674cdd09fb56ed9 (diff)
arch/x86: Enable SSE in bootblock_crt0.S
Don't write reserved bits in the Quark platform. Follow the previous boot behavior and just enable SSE. TEST=Build and run on Galileo Gen2 Change-Id: Ib3143eff02b2610b595bd666c10d70e43103ccda Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15128 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/x86')
-rw-r--r--src/arch/x86/bootblock_crt0.S8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S
index 7292b8b17c..9fbce5dbb5 100644
--- a/src/arch/x86/bootblock_crt0.S
+++ b/src/arch/x86/bootblock_crt0.S
@@ -41,14 +41,10 @@ bootblock_protected_mode_entry:
movd %eax, %mm1
movd %edx, %mm2
-#if !IS_ENABLED(CONFIG_SSE)
+#if IS_ENABLED(CONFIG_SSE)
enable_sse:
- mov %cr0, %eax
- and $~CR0_EM, %ax /* Clear coprocessor emulation CR0.EM */
- or $CR0_MP, %ax /* Set coprocessor monitoring CR0.MP */
- mov %eax, %cr0
mov %cr4, %eax
- or $(CR4_OSFXSR | CR4_OSXMMEXCPT), %ax
+ or $CR4_OSFXSR, %ax
mov %eax, %cr4
#endif /* IS_ENABLED(CONFIG_SSE) */