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authorSubrata Banik <subratabanik@google.com>2022-01-03 19:12:55 +0000
committerPaul Fagerburg <pfagerburg@chromium.org>2022-01-14 00:33:14 +0000
commitad50b40eed3f7f235e848a2382ffbee6a51d1755 (patch)
treeb8791e9c965c0b89d92e6d70d1635b99e184ba7a /src/arch/x86/tables.c
parenta2f51f222549035b27578cb084e13219443ca4b6 (diff)
soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` config
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/arch/x86/tables.c')
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