Improving BKDG implementation of P-states,

CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

bits 13 - 15 of F3xd4 (StutterScrubEn, CacheFlushImmOnAllHalt and MTC1eEn
are reserved for revisions D0 and earlier, so whe should not set them
to 0 in fidvid.c config_clk_power_ctrl_reg0(...), called from prep_fid_change.
For revisions > D0 (when we support them) it is ok not ot clear them,
because they are documented as 0 on reset. bit 12 should be left alone
according to BKDG. Should I set 11:8 ClkRampHystSel to 0 in the mask
too, just to indicate we're touching them ? We'll OR them to 1111 anyway...

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

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