diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-10-30 11:53:38 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2014-12-05 09:20:41 +0100 |
| commit | 3cf6aea871e4b5929959124356a7775ff21d65ac (patch) | |
| tree | 2b162d608dc0ebb6b102bda94d474d11666f7c15 /src/arch/x86/init | |
| parent | c3d49984f6fadbc82bc607851e3236191fe551fd (diff) | |
x86: Update the check for Forbidden global variables
Add a section .illegal_globals to romstage and check that the section does not
contain any variables while creating romstage.
[pg: Handle individual AGESA special cases in the
linker script instead of whitelisting everything
remotely AGESA related in the Makefile.]
Change-Id: I866681f51a44bc21770d32995c281b556a90c153
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7306
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/x86/init')
| -rw-r--r-- | src/arch/x86/init/romstage.ld | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index d6eb5111ef..99bcc8e748 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -65,5 +65,20 @@ SECTIONS preram_cbmem_console = .; } + /* Global variables are not allowed in romstage + * This section is checked during stage creation to ensure + * that there are no global variables present + */ + + . = 0xffffff00; + .illegal_globals . : { + *(EXCLUDE_FILE (*/libagesa.*.a: */buildOpts.romstage.o */agesawrapper.romstage.o */cpu/amd/agesa/*.romstage.o */vendorcode/amd/agesa/* */vendorcode/amd/cimx/*) .data) + *(.data.*) + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + } + _bogus = ASSERT((SIZEOF(.car.data) + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); } |