diff options
author | Julius Werner <jwerner@chromium.org> | 2017-04-17 18:16:39 -0700 |
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committer | Julius Werner <jwerner@chromium.org> | 2017-05-30 22:19:50 +0200 |
commit | cd6b22f9a02a7e21b39cc8a68d7ceb2f90a0815b (patch) | |
tree | a434d0931f97f532dc68615e22fec39dd217bec2 /src/arch/x86/include | |
parent | a92851939cffcfa11d3abf80cc910a43bb48e6b0 (diff) |
arch: Unify basic cache clearing API
Caching is a very architecture-specific thing, but most architectures
have a cache in general. Therefore it can be useful to have a generic
architecture-independent API to perform simple cache management tasks
from common code.
We have already standardized on the dcache_clean/invalidate naming
scheme that originally comes from ARM in libpayload, so let's just do
the same for coreboot. Unlike libpayload, there are other things than
just DMA coherency we may want to achieve with those functions, so
actually implement them for real even on architectures with
cache-snooping DMA like x86. (In the future, we may find applications
like this in libpayload as well and should probably rethink the API
there... maybe move the current functionality to a separate
dma_map/unmap API instead. But that's beyond scope of this patch.)
Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/arch/x86/include')
-rw-r--r-- | src/arch/x86/include/arch/cache.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h index 687d3bf9d3..9f7cda2643 100644 --- a/src/arch/x86/include/arch/cache.h +++ b/src/arch/x86/include/arch/cache.h @@ -31,6 +31,9 @@ #ifndef ARCH_CACHE_H #define ARCH_CACHE_H +#include <arch/early_variables.h> +#include <cpu/x86/cache.h> + /* * For the purposes of the currently executing CPU loading code that will be * run there aren't any cache coherency operations required. This just provides @@ -38,4 +41,21 @@ */ static inline void cache_sync_instructions(void) {} +/* Executing WBINVD when running out of CAR would not be good, prevent that. */ +static inline void dcache_clean_invalidate_all(void) +{ + if (!car_active()) + wbinvd(); +} +static inline void dcache_clean_all(void) +{ + /* x86 doesn't have a "clean without invalidate", fall back to both. */ + dcache_clean_invalidate_all(); +} +static inline void dcache_invalidate_all(void) +{ + if (!car_active()) + invd(); +} + #endif /* ARCH_CACHE_H */ |