diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-02-15 11:04:15 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-16 07:05:46 +0000 |
| commit | ba00d10c41d1df1ca8a5eadc95a40430fbd059c5 (patch) | |
| tree | 76b7c0d4896f3fd23baaa7f2cc8591a636b7e529 /src/arch/x86/include | |
| parent | 4e619b2c5c4732eb124b2909311abeb9e136cbd3 (diff) | |
arch/x86/postcar_loader.c: Reduce the scope of functions
Some functions are only called locally.
Change-Id: I96a4e40a225536f62abb2a15c55d333b8604e8cc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/arch/x86/include')
| -rw-r--r-- | src/arch/x86/include/arch/romstage.h | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 7a2a41773b..5951766a3c 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -21,12 +21,6 @@ struct postcar_frame { }; /* - * Initialize postcar_frame object. - * Returns 0 on success, < 0 on error. - */ -int postcar_frame_init(struct postcar_frame *pcf); - -/* * Add variable MTRR covering the provided range with MTRR type. */ void postcar_frame_add_mtrr(struct postcar_frame *pcf, @@ -52,17 +46,6 @@ void fill_postcar_frame(struct postcar_frame *pcf); void prepare_and_run_postcar(struct postcar_frame *pcf); /* - * Load and run a program that takes control of execution that - * tears down CAR and loads ramstage. The postcar_frame object - * indicates how to set up the frame. If caching is enabled at - * the time of the call it is up to the platform code to handle - * coherency with dirty lines in the cache using some mechanism - * such as platform_prog_run() because run_postcar_phase() - * utilizes prog_run() internally. - */ -void run_postcar_phase(struct postcar_frame *pcf); - -/* * Systems without a native coreboot cache-as-ram teardown may implement * this to use an alternate method. */ |