summaryrefslogtreecommitdiff
path: root/src/arch/x86/include/cf9_reset.h
diff options
context:
space:
mode:
authorCliff Huang <cliff.huang@intel.com>2024-08-19 10:03:10 -0700
committerFelix Held <felix-coreboot@felixheld.de>2024-08-22 13:25:40 +0000
commit1c6548d5ccfcc550b209ac9cef401883ffdc34ff (patch)
treec005a0e4fd72b5de785306f1e16493e81d8dcf25 /src/arch/x86/include/cf9_reset.h
parent2d4afd8fd99b46e9f1971ef9156d4cb72a53eddf (diff)
soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
These field defines are SOC-specific. The AUX bias virtual wire field positons are shifted in PTL. In MTL SOC and older: 7:0 GROUP_ID Group ID in PCH GPIO 10:8 BIT_NUM Data bit Position in PCH GPIO 23:16 VW_INDEX VW Index in PCH GPIO In PTL SOC: 15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID 18:16 BIT_NUM Data bit Position in PCH GPIO 31:24 VW_INDEX VW Index in PCH GPIO BUG=361048817 TEST=boot to OS and use iotools to read AUX Bias Ctrl register to verify the group ID, bit number, and vw index. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83980 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Diffstat (limited to 'src/arch/x86/include/cf9_reset.h')
0 files changed, 0 insertions, 0 deletions